test.sim.qmsg

TCC221图象传感器和FPGA实现图象采集 开发环境是quartus

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Simulator Quartus II " "Info: Running Quartus II Simulator" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Jun 13 21:22:26 2008 " "Info: Processing started: Fri Jun 13 21:22:26 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sim --read_settings_files=on --write_settings_files=off test -c test " "Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off test -c test" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISDB_SOURCE_VECTOR_FILE_USED" "E:/fifo/test.vwf " "Info: Using vector source file \"E:/fifo/test.vwf\"" {  } {  } 0 0 "Using vector source file \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISDB_OVERWRITE_WAVEFORM_INPUTS_WITH_SIMULATION_OUTPUTS" "" "Info: Overwriting simulation input file with simulation results" { { "Info" "ISDB_SOURCE_VECTOR_FILE_BACKUP" "test.vwf test.sim_ori.vwf " "Info: A backup of test.vwf called test.sim_ori.vwf has been created in the db folder" {  } {  } 0 0 "A backup of %1!s! called %2!s! has been created in the db folder" 0 0 "" 0}  } {  } 0 0 "Overwriting simulation input file with simulation results" 0 0 "" 0}
{ "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_FOUND" "" "Info: Inverted registers were found during simulation" { { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|test\|pr\[0\] " "Info: Register: \|test\|pr\[0\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|test\|pr\[1\] " "Info: Register: \|test\|pr\[1\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|test\|pr\[2\] " "Info: Register: \|test\|pr\[2\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|test\|pr\[3\] " "Info: Register: \|test\|pr\[3\]" {  } {  } 0 0 "Register: %1!s!" 0 0 "" 0}  } {  } 0 0 "Inverted registers were found during simulation" 0 0 "" 0}
{ "Info" "IEDS_MAX_TRANSITION_COUNT" "" "Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled" { { "Info" "IEDS_MAX_TRANSITION_COUNT_EXP" "" "Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements." {  } {  } 0 0 "Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements." 0 0 "" 0}  } {  } 0 0 "Option to preserve fewer signal transitions to reduce memory requirements is enabled" 0 0 "" 0}
{ "Info" "IEDS_SUB_SIMULATION_COUNT" "1 " "Info: Simulation partitioned into 1 sub-simulations" {  } {  } 0 0 "Simulation partitioned into %1!d! sub-simulations" 0 0 "" 0}
{ "Info" "ISIM_SIM_SIMULATION_COVERAGE" "     87.50 % " "Info: Simulation coverage is      87.50 %" {  } {  } 0 0 "Simulation coverage is %1!s!" 0 0 "" 0}
{ "Info" "ISIM_SIM_NUMBER_OF_TRANSITION" "1144 " "Info: Number of transitions in simulation is 1144" {  } {  } 0 0 "Number of transitions in simulation is %1!s!" 0 0 "" 0}
{ "Info" "ISDB_SDB_PROMOTE_WRITE_BINARY_VECTOR" "test.vwf " "Info: Vector file test.vwf is saved in VWF text format. You can compress it into CVWF format in order to reduce file size. For more details please refer to the Quartus II Help." {  } {  } 0 0 "Vector file %1!s! is saved in VWF text format. You can compress it into CVWF format in order to reduce file size. For more details please refer to the Quartus II Help." 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Simulator 0 s 0 s Quartus II " "Info: Quartus II Simulator was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "114 " "Info: Allocated 114 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Jun 13 21:22:28 2008 " "Info: Processing ended: Fri Jun 13 21:22:28 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}