fifo.map.summary

来自「TCC221图象传感器和FPGA实现图象采集 开发环境是quartus」· SUMMARY 代码 · 共 15 行

Analysis & Synthesis Status : Successful - Wed Jun 18 16:22:22 2008
Quartus II Version : 7.1 Build 156 04/30/2007 SJ Full Version
Revision Name : fifo
Top-level Entity Name : fifo
Family : Cyclone III
Total logic elements : 13
    Total combinational functions : 13
    Dedicated logic registers : 9
Total registers : 9
Total pins : 21
Total virtual pins : 0
Total memory bits : 128
Embedded Multiplier 9-bit elements : 0
Total PLLs : 0