📄 watch.rpt
字号:
Total: 8 9 25 8 8 23 26 0 24 1 24 12 16 16 16 24 8 8 24 32 16 16 16 2 10 8 0 17 2 8 16 8 16 15 15 8 8 16 16 16 1 8 16 8 2 8 2 16 16 8 8 8 20 662/0
Device-Specific Information: d:\watch\watch.rpt
watch
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
183 - - - -- INPUT G ^ 0 0 0 0 clk
95 - - - 09 INPUT ^ 0 0 0 30 clock
94 - - - 13 INPUT ^ 0 0 0 3 clr
97 - - - 07 INPUT ^ 0 0 0 28 data
99 - - - 06 INPUT ^ 0 0 0 1 h_add
101 - - - 04 INPUT ^ 0 0 0 2 hclock
100 - - - 05 INPUT ^ 0 0 0 1 m_add
102 - - - 03 INPUT ^ 0 0 0 3 mclock
103 - - - 02 INPUT ^ 0 0 0 4 pause
80 - - - -- INPUT G ^ 0 0 0 0 scanclk
96 - - - 08 INPUT ^ 0 0 0 35 sclock
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\watch\watch.rpt
watch
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
195 - - - 39 OUTPUT 0 1 0 0 leda0
196 - - - 41 OUTPUT 0 1 0 0 leda1
197 - - - 43 OUTPUT 0 1 0 0 leda2
198 - - - 44 OUTPUT 0 1 0 0 leda3
199 - - - 45 OUTPUT 0 1 0 0 leda4
200 - - - 46 OUTPUT 0 1 0 0 leda5
202 - - - 47 OUTPUT 0 1 0 0 leda6
203 - - - 48 OUTPUT 0 0 0 0 leda7
175 - - - 22 OUTPUT 0 1 0 0 led0
176 - - - 23 OUTPUT 0 1 0 0 led1
177 - - - 24 OUTPUT 0 1 0 0 led2
179 - - - 25 OUTPUT 0 1 0 0 led3
180 - - - 26 OUTPUT 0 1 0 0 led4
186 - - - 27 OUTPUT 0 1 0 0 led5
187 - - - 28 OUTPUT 0 1 0 0 led6
189 - - - 30 OUTPUT 0 0 0 0 led7
119 - - H -- OUTPUT 0 1 0 0 music
170 - - - 19 OUTPUT 0 1 0 0 row0
172 - - - 20 OUTPUT 0 1 0 0 row1
173 - - - 21 OUTPUT 0 1 0 0 row2
174 - - - 22 OUTPUT 0 1 0 0 row3
190 - - - 33 OUTPUT 0 1 0 0 row4
191 - - - 35 OUTPUT 0 1 0 0 row5
192 - - - 37 OUTPUT 0 1 0 0 row6
193 - - - 38 OUTPUT 0 1 0 0 row7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\watch\watch.rpt
watch
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 4 - H 04 AND2 0 3 0 3 |LPM_ADD_SUB:300|addcore:adder|:83
- 2 - H 04 AND2 0 3 0 4 |LPM_ADD_SUB:300|addcore:adder|:91
- 4 - H 06 AND2 0 2 0 1 |LPM_ADD_SUB:300|addcore:adder|:95
- 6 - H 06 AND2 0 4 0 2 |LPM_ADD_SUB:300|addcore:adder|:103
- 1 - G 03 AND2 0 2 0 3 |LPM_ADD_SUB:357|addcore:adder|:59
- 7 - G 03 AND2 0 2 0 1 |LPM_ADD_SUB:357|addcore:adder|:63
- 5 - G 03 AND2 0 3 0 1 |LPM_ADD_SUB:357|addcore:adder|:67
- 5 - G 06 AND2 0 2 0 1 |LPM_ADD_SUB:525|addcore:adder|:79
- 3 - G 06 AND2 0 3 0 4 |LPM_ADD_SUB:525|addcore:adder|:83
- 5 - G 19 AND2 0 2 0 1 |LPM_ADD_SUB:525|addcore:adder|:87
- 7 - G 19 AND2 0 3 0 1 |LPM_ADD_SUB:525|addcore:adder|:91
- 2 - G 19 AND2 0 4 0 2 |LPM_ADD_SUB:525|addcore:adder|:95
- 3 - G 09 AND2 0 2 0 3 |LPM_ADD_SUB:525|addcore:adder|:99
- 7 - G 09 AND2 0 2 0 1 |LPM_ADD_SUB:525|addcore:adder|:103
- 5 - G 09 AND2 0 3 0 1 |LPM_ADD_SUB:525|addcore:adder|:107
- 8 - J 25 AND2 0 2 0 1 |LPM_ADD_SUB:1123|addcore:adder|:55
- 7 - J 25 AND2 0 3 0 1 |LPM_ADD_SUB:1123|addcore:adder|:59
- 2 - J 13 AND2 0 2 0 1 |LPM_ADD_SUB:1447|addcore:adder|:55
- 8 - J 18 AND2 0 2 0 1 |LPM_ADD_SUB:1476|addcore:adder|:55
- 7 - J 18 AND2 0 3 0 1 |LPM_ADD_SUB:1476|addcore:adder|:59
- 1 - B 41 AND2 0 2 0 1 |LPM_ADD_SUB:1858|addcore:adder|:55
- 5 - B 05 OR2 ! 0 2 0 3 |LPM_ADD_SUB:1887|addcore:adder|:55
- 6 - B 05 AND2 0 2 0 1 |LPM_ADD_SUB:1887|addcore:adder|:59
- 2 - C 38 AND2 0 3 0 1 |LPM_ADD_SUB:2210|addcore:adder|:59
- 2 - C 47 AND2 0 2 0 2 |LPM_ADD_SUB:2273|addcore:adder|:55
- 7 - C 27 AND2 0 2 0 1 |LPM_ADD_SUB:2364|addcore:adder|:55
- 5 - C 51 AND2 0 3 0 1 |LPM_ADD_SUB:2364|addcore:adder|:59
- 8 - B 47 AND2 0 3 0 1 |LPM_ADD_SUB:2768|addcore:adder|:59
- 1 - B 33 AND2 0 2 0 2 |LPM_ADD_SUB:2797|addcore:adder|:55
- 6 - J 03 AND2 0 2 0 1 |LPM_ADD_SUB:3140|addcore:adder|:55
- 5 - J 07 AND2 0 2 0 3 |LPM_ADD_SUB:3203|addcore:adder|:55
- 4 - J 07 OR2 0 3 0 2 |LPM_ADD_SUB:3203|addcore:adder|:69
- 3 - B 12 AND2 0 2 0 1 |LPM_ADD_SUB:3403|addcore:adder|:55
- 1 - B 11 OR2 ! 0 2 0 3 |LPM_ADD_SUB:3432|addcore:adder|:55
- 2 - B 11 AND2 0 2 0 1 |LPM_ADD_SUB:3432|addcore:adder|:59
- 3 - A 52 OR2 0 4 0 1 |LPM_ADD_SUB:4496|addcore:adder|pcarry2
- 2 - A 32 AND2 s 0 3 0 1 |LPM_ADD_SUB:4496|addcore:adder|~79~1
- 5 - A 52 OR2 0 4 0 1 |LPM_ADD_SUB:4496|addcore:adder|:87
- 6 - B 52 OR2 0 4 0 1 |LPM_ADD_SUB:4883|addcore:adder|pcarry2
- 8 - B 52 OR2 0 4 0 1 |LPM_ADD_SUB:4883|addcore:adder|:81
- 4 - B 52 OR2 0 4 0 1 |LPM_ADD_SUB:4883|addcore:adder|:82
- 2 - B 52 OR2 0 4 0 1 |LPM_ADD_SUB:4883|addcore:adder|:87
- 8 - A 39 AND2 0 2 0 1 |LPM_ADD_SUB:6974|addcore:adder|:55
- 6 - A 39 AND2 0 3 0 1 |LPM_ADD_SUB:6974|addcore:adder|:59
- 5 - A 42 AND2 0 2 0 2 |LPM_ADD_SUB:7003|addcore:adder|:55
- 1 - B 38 OR2 ! 0 2 0 3 |LPM_ADD_SUB:7122|addcore:adder|:55
- 1 - B 39 OR2 ! 0 2 0 2 |LPM_ADD_SUB:7122|addcore:adder|:59
- 5 - B 32 OR2 ! 0 2 0 1 |LPM_ADD_SUB:7265|addcore:adder|:55
- 5 - H 07 OR2 0 2 0 2 |LPM_ADD_SUB:7645|addcore:adder|:67
- 3 - H 07 OR2 0 3 0 5 |LPM_ADD_SUB:7645|addcore:adder|:68
- 4 - H 07 OR2 0 4 0 5 |LPM_ADD_SUB:7645|addcore:adder|:69
- 2 - F 17 AND2 0 2 0 3 |LPM_ADD_SUB:7678|addcore:adder|:55
- 4 - F 17 AND2 0 3 0 1 |LPM_ADD_SUB:7678|addcore:adder|:59
- 3 - F 09 OR2 0 2 0 2 |LPM_ADD_SUB:7703|addcore:adder|:67
- 4 - F 16 OR2 0 3 0 2 |LPM_ADD_SUB:7703|addcore:adder|:68
- 6 - F 09 OR2 0 4 0 2 |LPM_ADD_SUB:7703|addcore:adder|:69
- 7 - A 39 OR2 0 4 0 2 |LPM_MULT:4475|multcore:mult_core|romout0_1
- 3 - A 20 OR2 s 0 4 0 1 |LPM_MULT:4475|multcore:mult_core|romout0_2~1
- 5 - A 20 OR2 s 0 4 0 1 |LPM_MULT:4475|multcore:mult_core|romout0_2~2
- 1 - A 20 OR2 0 3 0 1 |LPM_MULT:4475|multcore:mult_core|romout0_2
- 7 - A 15 OR2 0 4 0 1 |LPM_MULT:4475|multcore:mult_core|romout0_4
- 4 - A 20 AND2 ! 0 4 0 1 |LPM_MULT:4475|multcore:mult_core|:1280
- 8 - A 20 AND2 ! 0 4 0 1 |LPM_MULT:4475|multcore:mult_core|:1396
- 4 - A 15 AND2 ! 0 4 0 1 |LPM_MULT:4475|multcore:mult_core|:1424
- 7 - A 20 AND2 ! 0 4 0 1 |LPM_MULT:4475|multcore:mult_core|:1453
- 6 - A 20 AND2 ! 0 4 0 1 |LPM_MULT:4475|multcore:mult_core|:1512
- 1 - A 15 AND2 s 0 2 0 1 |LPM_MULT:4475|multcore:mult_core|~1541~1
- 5 - A 15 OR2 0 4 0 1 |LPM_MULT:4475|multcore:mult_core|:1559
- 8 - A 15 OR2 s 0 4 0 1 |LPM_MULT:4475|multcore:mult_core|~1562~1
- 2 - A 20 OR2 0 4 0 1 |LPM_MULT:4475|multcore:mult_core|:1562
- 4 - A 39 OR2 0 4 0 1 |LPM_MULT:4475|multcore:mult_core|:1613
- 1 - B 29 OR2 s 0 4 0 1 |LPM_MULT:4862|multcore:mult_core|romout0_1~1
- 4 - B 29 OR2 0 4 0 2 |LPM_MULT:4862|multcore:mult_core|romout0_1
- 8 - B 27 AND2 0 2 0 1 |LPM_MULT:4862|multcore:mult_core|romout0_2
- 6 - B 37 OR2 s 0 4 0 1 |LPM_MULT:4862|multcore:mult_core|romout0_4~1
- 7 - B 52 OR2 0 3 0 1 |LPM_MULT:4862|multcore:mult_core|romout0_4
- 3 - B 45 OR2 s 0 4 0 1 |LPM_MULT:4862|multcore:mult_core|~1223~1
- 4 - B 45 OR2 ! 0 4 0 1 |LPM_MULT:4862|multcore:mult_core|:1223
- 1 - B 52 AND2 ! 0 4 0 2 |LPM_MULT:4862|multcore:mult_core|:1280
- 6 - B 45 AND2 s 0 4 0 1 |LPM_MULT:4862|multcore:mult_core|~1308~1
- 5 - B 29 AND2 s 0 3 0 1 |LPM_MU⌨️ 快捷键说明
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