decoder3_8.vhd

来自「3-8decoder实现fpga功能」· VHDL 代码 · 共 32 行

library ieee;  
use ieee.std_logic_1164.all;

entity decoder3_8 is  
port(a,b,c,g1,g2a,g2b:in std_logic;
           y:out std_logic_vector(7 downto 0));
end ;

architecture rtl of decoder3_8 is  
 signal dz:std_logic_vector(2 downto 0);   
begin 
 dz<=c&b&a;
process(dz,g1,g2a,g2b )
begin
if (g1='1' and g2a='0' and g2b='0') then
  case dz is
   when "000"=>y<="11111110";
   when "001"=>y<="11111101";
   when "010"=>y<="11111011";
   when "011"=>y<="11110111";
   when "100"=>y<="11101111";
   when "101"=>y<="11011111";
   when "110"=>y<="10111111";
   when "111"=>y<="01111111";
   when others=>y<="XXXXXXXX";
  end case;
else
 y<="11111111";
end if;
end process;
end;