logbooth.v

来自「设计了一种利用逻辑电路来实现booth乘法的电路。简单明了」· Verilog 代码 · 共 46 行

module mul(M,Q,Cout);
   input signed [15:0] M,Q;
   output signed [31:0] Cout;
   
   reg signed [31:0] Cout,rM1,rM2,rM3,rM4;
   reg[3:0] n;
   reg signed [15:0] rQ;
   reg signed [15:0] M2,M3,M4;
   reg C;

   always @(M or Q)
     begin
      {rQ,C}={Q,1'b0};
        //rM1<=M;
          rM1=M;
           M3=(M<<1);
           rM3=M3;
           M2=((~M)+16'h0001);
         //rM2<=M2;
          rM2=M2;
          M4=((~(M<<1)+16'h0001));
          rM4=M4;
          Cout=32'b0;

      for(n=0;n<4'b1001;n=n+1)
         begin
              case({rQ[1],rQ[0],C})
                 3'b000: Cout=Cout;
                 3'b001: Cout=Cout+rM1;
                 3'b010: Cout=Cout+rM1;
                 3'b011: Cout=Cout+rM3;
                 3'b100: Cout=Cout+rM4;
                 3'b101: Cout=Cout+rM2;
                 3'b110: Cout=Cout+rM2;
                 3'b111: Cout=Cout;
            default: Cout=Cout;
          endcase
             {rQ,C}={rQ,C}>>2;
             rM1=rM1<<2;
             rM2=rM2<<2;
             rM3=rM3<<2;
             rM4=rM4<<2;
           end
       end
endmodule