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📄 pcm_initial.c

📁 PCM 脉冲编码调制的C源代码
💻 C
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//-------------------------------------------------------- 
#include "codec.h"
#include "reg5509a.h"
#include "lcd.h"

extern unsigned int key_flag;
unsigned int cpld_ctrl_back = 0xef;
//-------------------------------------------------------- 
#define AIC23_ADDR 0x34

extern void delayMs_SYS(unsigned int msecond);
extern void delayUs_SYS(unsigned int usecond);

extern void mcbsp2_init(void);
extern void mcbsp2_write_rdy(unsigned int out_data1,unsigned int out_data2);//MCBSP1发送一个数据32位
extern void mcbsp2_read_rdy(void);
extern void mcbsp2_open(void);
extern void mcbsp2_close(void);
extern void Delay(int numbers);       
/****************************************************************/
//-------------------------------------------------------------
void mcbsp2_init(void)
{
  SPCR1_2 = 0;
  SPCR2_2 = 0;
  delayUs_SYS(10);
  RCR1_2 = 0x00A0;
  RCR2_2 = 0x00A0;
  XCR1_2 = 0x00A0;
  XCR2_2 = 0x00A0;
  PCR2 = 0x000D;
}


void mcbsp2_write_rdy(unsigned int out_data1,unsigned int out_data2) 
{  
  while ((SPCR2_2 &0x0002)==0) 
   {
    ;      
   };  
  DXR2_2= out_data2; 
  DXR1_2= out_data1;
}

void mcbsp2_read_rdy(void) 
{  
   while((SPCR1_2 & 0x0002) == 0);
}


void mcbsp2_open()
{
   SPCR1_2 = SPCR1_2 | 0x0001;
   SPCR2_2 = SPCR2_2 | 0x0001;
}

void mcbsp2_close()
{
    SPCR1_2 = SPCR1_2 &0xFFFE;
    SPCR2_2 = SPCR2_2 &0xFFFE;
}

//----------------------------------------------------------------

void AIC23_CLK(unsigned int flag)
{
	if(flag ==0) cpld_ctrl_back &= ~B5_MSK; 
	else cpld_ctrl_back |= B5_MSK; 
	CPLD_CTRL_REG = cpld_ctrl_back;
}
void AIC23_DIN(unsigned int flag)
{
	if(flag ==0) cpld_ctrl_back &= ~B6_MSK; 
	else cpld_ctrl_back |= B6_MSK; 
	CPLD_CTRL_REG = cpld_ctrl_back;
}
void AIC23_DIN_EN(unsigned int flag)
{
	if(flag ==0) cpld_ctrl_back &= ~B7_MSK; 
	else cpld_ctrl_back |= B7_MSK; 
	CPLD_CTRL_REG = cpld_ctrl_back;
}

//----------------------------------------------------------------
void SCLK_DIN23(unsigned int flag_clk,unsigned int flag_din,unsigned int flag_din_en)
{
	if(flag_clk==0) 
		cpld_ctrl_back &= ~B5_MSK; 
	else 
		cpld_ctrl_back |= B5_MSK; 
		
	if(flag_din==0) 
		cpld_ctrl_back &= ~B6_MSK; 
	else 
		cpld_ctrl_back |= B6_MSK; 	
	
	if(flag_din_en == 0)
		cpld_ctrl_back &= ~B7_MSK; 
	else 
		cpld_ctrl_back |= B7_MSK; 
				
	CPLD_CTRL_REG = cpld_ctrl_back;				
}
//----------------------------------------------------------------
void set_aic23_sci_mode()
{
//	AIC23_CS(0);
	AIC23_DIN_EN(1);
	AIC23_DIN(1);
	AIC23_CLK(1);
	delayMs_SYS(3);
	AIC23_DIN_EN(1);
	AIC23_DIN(1);
	delayMs_SYS(10);	
}
//----------------------------------------------------------------
void send_aic23_bit(unsigned int dat)
{
	delayMs_SYS(2);
	SCLK_DIN23(0,dat,1);
	delayMs_SYS(2);
	AIC23_CLK(1);
}
//----------------------------------------------------------------

void send_aic23_ctrl_reg(unsigned int dat)
{
	unsigned int temp_dat;
	unsigned int flag;
	
	AIC23_CLK(1);
	delayMs_SYS(3);
	AIC23_DIN_EN(1);
	AIC23_DIN(1);
	delayMs_SYS(10);
	
	AIC23_DIN(0);		//start
	delayMs_SYS(3);
	AIC23_CLK(0);
	delayMs_SYS(3);
	
	//SEND ADDRESS
	temp_dat = (AIC23_ADDR | 0x00);		//write only
	{
		flag = 0x80;
		
		AIC23_DIN((flag & temp_dat));
		delayMs_SYS(2);
		AIC23_CLK(1);
			
		for(flag = 0x40;flag != 0;flag >>=1)	
		{	
			send_aic23_bit(flag & temp_dat);
		}
	}
	SCLK_DIN23(0,0,0);
	delayMs_SYS(2);
	AIC23_CLK(1);
	delayMs_SYS(2);					
	AIC23_CLK(0);						
	
	//SEND HIGNT BYTE
	temp_dat = (dat >> 8);
	{
		flag = 0x80;
		SCLK_DIN23(0,(flag & temp_dat),1);
		
		delayMs_SYS(2);
		AIC23_CLK(1);
			
		for(flag = 0x40;flag != 0;flag >>=1)	
		{	
			send_aic23_bit(flag & temp_dat);
		}
	}
	SCLK_DIN23(0,0,0);
	delayMs_SYS(2);
	AIC23_CLK(1);
	delayMs_SYS(2);						
	AIC23_CLK(0);						
	
	//SEND LOW BYTE
	temp_dat = dat;
	{
		flag = 0x80;	
		SCLK_DIN23(0,(flag & temp_dat),1);
		delayMs_SYS(2);
		AIC23_CLK(1);
			
		for(flag = 0x40;flag != 0;flag >>=1)	
		{	
			send_aic23_bit(flag & temp_dat);
		}
	}
	SCLK_DIN23(0,0,0);
	delayMs_SYS(2);
	AIC23_CLK(1);
	delayMs_SYS(2);					
	AIC23_CLK(0);					
	
	AIC23_DIN(0);
	AIC23_DIN_EN(1);
	delayMs_SYS(2);
	
	AIC23_CLK(1);
	delayMs_SYS(1);
	AIC23_DIN(1);
	
}

void reset_aic23()
{
  	send_aic23_ctrl_reg(0x1e00);  //REG10  RESET AIC23
  	delayUs_SYS(100);
}

void PCM_SUB(void)
{
	reset_aic23();

                             
  	send_aic23_ctrl_reg(0x0117);  //REG0   Left line input channel volume control 
  	//send_aic23_ctrl_reg(0x0110);  //REG0   Left line input channel volume control 
  	asm(" nop ");              	//Address  (bits 15-9) 0000000 
                             	//LRS      (bits 8)           1          Left/right line simultaneous volume/mute update Enabled
                             	//LIM      (bits 7)            0         Left line input mute 0 = Normal
                             	//XX       (bits 6-5)           00       Reserved
                             	//LIV[4:0] (bits 4-0)              10111 Left line input volume control (10111 = 0 dB default)
                             	//-----0000 0001 0001 0111
                              
  	send_aic23_ctrl_reg(0x0317);  //REG1  Right Line Input Channel Volume Controlxxxxxxxx
  	//send_aic23_ctrl_reg(0x0310);  //REG1  Right Line Input Channel Volume Controlxxxxxxxx
  	asm(" nop ");              //Address  (bits 15-9) 0000001 
                             //RRS      (bits 8)           1          Left/right line simultaneous volume/mute update Enabled
                             //RIM      (bits 7)            0         Left line input mute 0 = Normal
                             //XX       (bits 6-5)           00       Reserved
                             //RIV[4:0] (bits 4-0)              10111 Left line input volume control (10111 = 0 dB default)
                             //-----0000 0011 0001 0111
  
  	//send_aic23_ctrl_reg(0x05f9);  //REG2 Left Channel Headphone Volume Control
  	send_aic23_ctrl_reg(0x043f);
  	asm(" nop ");              //Address  (bits 15-9) 0000010
                            //LRS      (bits 8)           1         Left/right headphone channel simultaneous volume/mute update 1 = Enabled
                             //LZC      (bits 7)            1        Left-channel zero-cross detect 0 = Off
                             //LHV[6:0] (bits 6-0)           1111001 Left Headphone volume control (1111001 = 0 dB default)
                             //-----0000 0101 1111 1001 
                             
  	//send_aic23_ctrl_reg(0x07f9);  //REG3 Right Channel Headphone Volume Control
  	send_aic23_ctrl_reg(0x0670);  //REG3 Right Channel Headphone Volume Control
  	asm(" nop ");              //Address  (bits 15-9) 0000011
                             //RLS      (bits 8)           1         Left/right headphone channel simultaneous volume/mute update 1 = Enabled
                             //RZC      (bits 7)            1        Left-channel zero-cross detect 0 = Off
                             //RHV[6:0] (bits 6-0)           1111001 Left Headphone volume control (1111001 = 0 dB default)
                             //-----0000 0111 1111 1001
 
 	// mcbsp2_write_rdy(0x0810); //选择线性输入 

  	//send_aic23_ctrl_reg(0x0814);  //选择麦克风输入
  	send_aic23_ctrl_reg(0x0815);  //选择麦克风输入
  	asm(" nop ");              //REG4 Analog Audio Path Control
                            //Address  (bits 15-9) 0000100
                             //X        (bits 8)           0         Reserved
                             //STA[1:0] (bits 7-6)          00       Sidetone attenuation 00 = –6 dB
                             //STE      (bits 5)              0      Sidetone enable 0 = Disabled
                             //DAC      (bits 4)               1     DAC select 1 = DAC selected
                             //BYP      (bits 3)                0    Bypass 0 = Disabled 1=Enabled,ONLY FOR TEST
                             //INSEL    (bits 2)                 0   Input select for ADC 0 = Line 
                             //MICM     (bits 1)                  0  Microphone mute 0 = Normal
                             //MICB     (bits 0)                   0 Microphone boost 0=OdB
                             //-----0000 1000 0001 0000
                             
  	send_aic23_ctrl_reg(0x0A01);  //REG5 Digital Audio Path Control
  	//send_aic23_ctrl_reg(0x0A05);  //REG5 Digital Audio Path Control
  	asm(" nop ");              //Address  (bits 15-9) 0000101
                             //X        (bits 8-4)         00000     Reserved
                             //DACM     (bits 3)                0    DAC soft mute 0 = Disabled
                             //DEEMP[1:0] (bits 2-1)             00  De-emphasis control 00 = Disabled
                             //ADCHP    (bits 0)                   1 ADC high-pass filter 1 = Enabled 
                             //----- 0000 1010 0000 0001
                                                          
  	send_aic23_ctrl_reg(0x0C00);  //REG6 Power Down Control
  	//send_aic23_ctrl_reg(0x0C01);  //REG6 Power Down Control
  	asm(" nop ");              //Address  (bits 15-9) 0000110
                             //X        (bits 8)           0         Reserved
                             //OFF      (bits 7)            0        Device power 0 = On
                             //CLK      (bits 6)             0       Clock 0 = On
                             //OSC      (bits 5)              0      Oscillator 0 = On
                             //OUT      (bits 4)               0     Outputs 0 = On
                             //DAC      (bits 3)                0    DAC 0 = On
                             //ADC      (bits 2)                 0   ADC 0 = On
                             //MIC      (bits 1)                  0  Microphone input 0 = On
                             //LINE     (bits 0)                   0 Line input 0 = On
                             //----- 0000 1100 0000 0000 
                             
  	send_aic23_ctrl_reg(0x0E73);  //REG7 Digital Audio Interface Format
  	asm(" nop ");              //Address  (bits 15-9) 0000111
                             //X        (bits 8-7)         00         Reserved
                             //MS       (bits 6)             1        Master/slave mode  1 = Master
                             //LRSWAP   (bits 5)              1       DAC left/right swap  1 = Enabled
                             //LRP      (bits 4)               1      DAC left/right phase,1 = Right channel on, LRCIN low; "DSP mode", 1 = MSB is available on 2nd BCLK rising edge after LRCIN rising edge
                             //IWL[1:0] (bits 3-2)              00    Input bit length 00 = 16 bit
                             //FOR[1:0] (bits 1-0)                11  Data format 11 = DSP format, frame sync followed by two data words           
                             //----- 0000 1110 0111 0011 
                         
  	
  
  	send_aic23_ctrl_reg(0x101C);//8KHZ采样频率
                         //REG8 Sample Rate Control 
  	asm(" nop ");        //Address  (bits 15-9) 0001000
                         //X        (bits 8)           0         Reserved 
                         //CLKOUT   (bits 7)            0        Clock input divider 0 = MCLK
                         //CLKIN    (bits 6)             0       Clock output divider 0 = MCLK
                         //SR[3:0]  (bits 5-2)            0011   MCLK = 12.288 MHz, sampling rates=8KHZ                        
                         //BOSR     (bits 1)                  0  Base oversampling rate Normal mode: 0 = 256 fs
                         //USB/Normal(bits 0)                  0 Clock mode select: 0 = Normal
                         //----- 0001 0000 0000 1100            
                             
  	send_aic23_ctrl_reg(0x1201);  //REG9 Digital Interface Activation
  	asm(" nop ");        //Address  (bits 15-9) 0001001
  	                     //X        (bits 8-1)         00000000  Reserved
                         //ACT      (bits 0)                   1 Activate interface 1 = Active
}


//-----------------------------------
unsigned int read_key()
{
	unsigned int temp_key;
	unsigned int r;
	unsigned int c;
			
	if(key_flag ==0)return 0;		
	temp_key = (KEY_DAT_REG | 0x80);
	switch(temp_key & 0xf0)
	{
		case 0xe0: r = 0x10;break;
		case 0xd0: r = 0x20;break;
		case 0xb0: r = 0x30;break;
		case 0x70: r = 0x40;break;
		default :r = 0;break;
	}
	
	switch(temp_key & 0x0f)
	{
		case 0x0e: c = 0x01;break;
		case 0x0d: c = 0x02;break;
		case 0x0b: c = 0x03;break;
		case 0x07: c = 0x04;break;
		default: c = 0;break;
	}
	
	key_flag = 0;
	IER0 |= 0x0004;
	if((r==0)|(c==0))return 0;
	return(r | c);
}

//--------------------结束----------------------------------------

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