reg5509a.h

PCM 脉冲编码调制的C源代码

#define MMCNBLK     (*(ioport unsigned int *)0x4809)//MMC Number of Blocks Register
#define MMCNBLC     (*(ioport unsigned int *)0x480a)//MMC Number of Blocks Counter Register
#define MMCDRR      (*(ioport unsigned int *)0x480b)//MMC Data Receive Register 
#define MMCDXR      (*(ioport unsigned int *)0x480c)//MMC Data Transmit Register
#define MMCCMD      (*(ioport unsigned int *)0x480d)//MMC Command Register
#define MMCARGL     (*(ioport unsigned int *)0x480e)//MMC Argument Register . Low
#define MMCARGH     (*(ioport unsigned int *)0x480f)//MMC Argument Register . High
#define MMCRSP0     (*(ioport unsigned int *)0x4810)//MMC Response Register 0
#define MMCRSP1     (*(ioport unsigned int *)0x4811)//MMC Response Register 1
#define MMCRSP2     (*(ioport unsigned int *)0x4812)//MMC Response Register 2
#define MMCRSP3     (*(ioport unsigned int *)0x4813)//MMC Response Register 3
#define MMCRSP4     (*(ioport unsigned int *)0x4814)//MMC Response Register 4
#define MMCRSP5     (*(ioport unsigned int *)0x4815)//MMC Response Register 5
#define MMCRSP6     (*(ioport unsigned int *)0x4816)//MMC Response Register 6
#define MMCRSP7     (*(ioport unsigned int *)0x4817)//MMC Response Register 7
#define MMCDRSP     (*(ioport unsigned int *)0x4818)//MMC Data Response Register
//--- #4819h IS RESERVED! //
#define MMCCIDX     (*(ioport unsigned int *)0x481a)//MMC Command Index Register

//------------------------------------------------------------------------	
    #else	  //否则是SD2，寄存器为下面的地址
//------------------------MMC/SD2 Module Registers------------------------				                               		                               		                               
#define MMCFCLK     (*(ioport unsigned int *)0x4c00)//MMC Function Clock Control Register   
#define MMCCTL      (*(ioport unsigned int *)0x4c01)//MMC Control Register
#define MMCCLK      (*(ioport unsigned int *)0x4c02)//MMC Clock Control Register
#define MMCST0      (*(ioport unsigned int *)0x4c03)//MMC Status Register 0
#define MMCST1      (*(ioport unsigned int *)0x4c04)//MMC Status Register 1
#define MMCIE       (*(ioport unsigned int *)0x4c05)//MMC Interrupt Enable Register
#define MMCTOR      (*(ioport unsigned int *)0x4c06)//MMC Response Time-Out Register
#define MMCTOD      (*(ioport unsigned int *)0x4c07)//MMC Data Read Time-Out Register
#define MMCBLEN     (*(ioport unsigned int *)0x4c08)//MMC Block Length Register
#define MMCNBLK     (*(ioport unsigned int *)0x4c09)//MMC Number of Blocks Register
#define MMCNBLC     (*(ioport unsigned int *)0x4c0a)//MMC Number of Blocks Counter Register
#define MMCDRR      (*(ioport unsigned int *)0x4c0b)//MMC Data Receive Register 
#define #MMCDXR     (*(ioport unsigned int *)0x4c0c)//MMC Data Transmit Register
#define MMCCMD      (*(ioport unsigned int *)0x4c0d)//MMC Command Register
#define MMCARGL     (*(ioport unsigned int *)0x4c0e)//MMC Argument Register . Low
#define MMCARGH     (*(ioport unsigned int *)0x4c0f)//MMC Argument Register . High
#define MMCRSP0     (*(ioport unsigned int *)0x4c10)//MMC Response Register 0
#define MMCRSP1     (*(ioport unsigned int *)0x4c11)//MMC Response Register 1
#define MMCRSP2     (*(ioport unsigned int *)0x4c12)//MMC Response Register 2
#define MMCRSP3     (*(ioport unsigned int *)0x4c13)//MMC Response Register 3
#define MMCRSP4     (*(ioport unsigned int *)0x4c14)//MMC Response Register 4
#define MMCRSP5     (*(ioport unsigned int *)0x4c15)//MMC Response Register 5
#define MMCRSP6     (*(ioport unsigned int *)0x4c16)//MMC Response Register 6
#define MMCRSP7     (*(ioport unsigned int *)0x4c17)//MMC Response Register 7
#define MMCDRSP     (*(ioport unsigned int *)0x4c18)//MMC Data Response Register
//--- #4c19h IS RESERVED! //
#define MMCCIDX     (*(ioport unsigned int *)0x4c1a)//MMC Command Index Register		
	
	 #endif	
//----------------------------USB Module Registers------------------------------
//#define #5800h                 // Reserved_usb
#define DMAC_O1         (*(ioport unsigned int *)0x5808)//Output Endpoint 1 DMA Context Register
#define DMAC_O2         (*(ioport unsigned int *)0x5810)//Output Endpoint 2 DMA Context Register
#define DMAC_O3         (*(ioport unsigned int *)0x5818)//Output Endpoint 3 DMA Context Register
#define DMAC_O4         (*(ioport unsigned int *)0x5820)//Output Endpoint 4 DMA Context Register
#define DMAC_O5         (*(ioport unsigned int *)0x5828)//Output Endpoint 5 DMA Context Register
#define DMAC_O6         (*(ioport unsigned int *)0x5830)//Output Endpoint 6 DMA Context Register
#define DMAC_O7         (*(ioport unsigned int *)0x5838)//Output Endpoint 7 DMA Context Register
//--------------------------------------------------------------------
//#define #5840H                 //Reserved_usb
#define DMAC_I1         (*(ioport unsigned int *)0x5848)//Input Endpoint 1 DMA Context Register
#define DMAC_I2         (*(ioport unsigned int *)0x5850)//Input Endpoint 2 DMA Context Register
#define DMAC_I3         (*(ioport unsigned int *)0x5858)//Input Endpoint 3 DMA Context Register
#define DMAC_I4         (*(ioport unsigned int *)0x5860)//Input Endpoint 4 DMA Context Register
#define DMAC_I5         (*(ioport unsigned int *)0x5868)//Input Endpoint 5 DMA Context Register
#define DMAC_I6         (*(ioport unsigned int *)0x5870)//Input Endpoint 6 DMA Context Register
#define DMAC_I7         (*(ioport unsigned int *)0x5878)//Input Endpoint 7 DMA Context Register
//--------------------------------------------------------------------
//#define #5880h, Data Buffers   //Contains X/Y data buffers for endpoints 1 – 7
#define OEB_0           (*(ioport unsigned int *)0x6680)//Output Endpoint 0 Buffer
#define IEB_0           (*(ioport unsigned int *)0x66c0)//Input Endpoint 0 Buffer
#define SUP_0           (*(ioport unsigned int *)0x6700)//Setup Packet for Endpoint 0
//--------------------------------------------------------------------
#define OEDB_1          (*(ioport unsigned int *)0x6708)//Output Endpoint 1 Descriptor Register Block
#define OEDB_2          (*(ioport unsigned int *)0x6701)//Output Endpoint 2 Descriptor Register Block
#define OEDB_3          (*(ioport unsigned int *)0x6718)//Output Endpoint 3 Descriptor Register Block
#define OEDB_4          (*(ioport unsigned int *)0x6720)//Output Endpoint 4 Descriptor Register Block
#define OEDB_5          (*(ioport unsigned int *)0x6728)//Output Endpoint 5 Descriptor Register Block
#define OEDB_6          (*(ioport unsigned int *)0x6730)//Output Endpoint 6 Descriptor Register Block
#define OEDB_7          (*(ioport unsigned int *)0x6738)//Output Endpoint 7 Descriptor Register Block

//#define #6740H                 //Reserved 
//--------------------------------------------------------------------   
#define IEDB_1          (*(ioport unsigned int *)0x6748)//Input Endpoint 1 Descriptor Register Block
#define IEDB_2          (*(ioport unsigned int *)0x6750)//Input Endpoint 2 Descriptor Register Block
#define IEDB_3          (*(ioport unsigned int *)0x6758)//Input Endpoint 3 Descriptor Register Block
#define IEDB_4          (*(ioport unsigned int *)0x6760)//Input Endpoint 4 Descriptor Register Block
#define IEDB_5          (*(ioport unsigned int *)0x6768)//Input Endpoint 5 Descriptor Register Block
#define IEDB_6          (*(ioport unsigned int *)0x6770)//Input Endpoint 6 Descriptor Register Block
#define IEDB_7          (*(ioport unsigned int *)0x6778)//Input Endpoint 7 Descriptor Register Block
//--------------------------------------------------------------------
#define IEPCNF_0        (*(ioport unsigned int *)0x6780)//Input Endpoint 0 Configuration
#define IEPBCNT_0       (*(ioport unsigned int *)0x6781)//Input Endpoint 0 Byte Count
#define OEPCNF_0        (*(ioport unsigned int *)0x6782)//Output Endpoint 0 Configuration
#define OEPBCNT_0       (*(ioport unsigned int *)0x6783)//Output Endpoint 0 Byte Count

//#define #6784~6790h            //Reserved 
//--------------------------------------------------------------------
#define GLOBCTL         (*(ioport unsigned int *)0x6791)//global control reg.
#define VECINT          (*(ioport unsigned int *)0x6792)//vector interrupt reg.
#define IEPINT          (*(ioport unsigned int *)0x6793)//input endpint interrupt reg.
#define OEPINT          (*(ioport unsigned int *)0x6794)//output endpoint interrupt reg.
#define IDMARINT        (*(ioport unsigned int *)0x6795)//input DMA reload interrupt reg.
#define ODMARINT        (*(ioport unsigned int *)0x6796)//output DMA reload interrupt reg.
#define IDMAGINT        (*(ioport unsigned int *)0x6797)//input DMA go interrupt reg.
#define ODMAGINT        (*(ioport unsigned int *)0x6798)//output DMA go interrupt reg.
#define IDMAMSK         (*(ioport unsigned int *)0x6799)//input DMA interrupt mask reg.
#define ODMAMSK         (*(ioport unsigned int *)0x679a)//output DMA interrupt mask reg.
#define IEDBMSK         (*(ioport unsigned int *)0x679b)//input EDB interrupt mask reg.
#define OEDBMSK         (*(ioport unsigned int *)0x679c)//output EDB interrupt mask register.
//--------------------------------------------------------------------
#define FNUML           (*(ioport unsigned int *)0x67f8)//frame number low register.
#define FNUMH           (*(ioport unsigned int *)0x67f9)//frame number high
#define PSOFTMR         (*(ioport unsigned int *)0x67fa)//PreSOF interrupt timer reg.
//--------------------------------------------------------------------
#define USBCTL          (*(ioport unsigned int *)0x67fc)// usb control register.
#define USBMSK          (*(ioport unsigned int *)0x67fd)// usb interrupt mask reg.
#define USBSTA          (*(ioport unsigned int *)0x67fe)// usb status reg.
#define FUNADR          (*(ioport unsigned int *)0x67ff)//function address reg.
#define USBIDLECTL      (*(ioport unsigned int *)0x7000)//usb idle ctrl and stats reg
//--------------------------------------------------------------------
//---------------Analog-to-Digital Controller (ADC) Registers---------
#define ADCCTL          (*(ioport unsigned int *)0x6800)//ADC Control Register
#define ADCDATA         (*(ioport unsigned int *)0x6801)//ADC Data Register
#define ADCCLKDIV       (*(ioport unsigned int *)0x6802)//ADC Function Clock Divider Register
#define ADCCLKCTL       (*(ioport unsigned int *)0x6803)//ADC Clock Control Register
//--------------------------------------------------------------------
//---------------External Bus Selection Register----------------------
#define EBSR            (*(ioport unsigned int *)0x6c00)//External Bus Selection Register
//--------------------------------------------------------------------
//********************************************************************

//********************************************************************
//--------------常量定义-------------------
//********************************************************************
#define B15_MSK   0x8000    //位15屏蔽或置位
#define B14_MSK   0x4000    //位14屏蔽或置位
#define B13_MSK   0x2000    //位13屏蔽或置位
#define B12_MSK   0x1000    //位12屏蔽或置位
#define B11_MSK   0x0800    //位11屏蔽或置位
#define B10_MSK   0x0400    //位10屏蔽或置位
#define B9_MSK    0x0200    //位9屏蔽或置位
#define B8_MSK    0x0100    //位8屏蔽或置位
#define B7_MSK    0x0080    //位7屏蔽或置位
#define B6_MSK    0x0040    //位6屏蔽或置位
#define B5_MSK    0x0020    //位5屏蔽或置位
#define B4_MSK    0x0010    //位4屏蔽或置位
#define B3_MSK    0x0008    //位3屏蔽或置位
#define B2_MSK    0x0004    //位2屏蔽或置位
#define B1_MSK    0x0002    //位1屏蔽或置位
#define B0_MSK    0x0001    //位0屏蔽或置位
//----------------------------------------------------------------
//--------------------以下空白----------------------
//********************************************************************