📄 reg5509a.h
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#define RCR2_0 (*(ioport unsigned int *)0x2806)//Receive Control Register 2, McBSP #0
#define RCR1_0 (*(ioport unsigned int *)0x2807)//Receive Control Register 1, McBSP #0
#define XCR2_0 (*(ioport unsigned int *)0x2808)//Transmit Control Register 2, McBSP #0
#define XCR1_0 (*(ioport unsigned int *)0x2809)//Transmit Control Register 1, McBSP #0
#define SRGR2_0 (*(ioport unsigned int *)0x280a)//Sample Rate Generator Register 2, McBSP #0
#define SRGR1_0 (*(ioport unsigned int *)0x280b)//Sample Rate Generator Register 1, McBSP #0
#define MCR2_0 (*(ioport unsigned int *)0x280c)//Multichannel Control Register 2, McBSP #0
#define MCR1_0 (*(ioport unsigned int *)0x280d)//Multichannel Control Register 1, McBSP #0
//--------------------------------------------------------------------
#define RCERA_0 (*(ioport unsigned int *)0x280e)//Receive Channel Enable Register Partition A, McBSP #0
#define RCERB_0 (*(ioport unsigned int *)0x280f)//Receive Channel Enable Register Partition B, McBSP #0
#define XCERA_0 (*(ioport unsigned int *)0x2810)//Transmit Channel Enable Register Partition A, McBSP #0
#define XCERB_0 (*(ioport unsigned int *)0x2811)//Transmit Channel Enable Register Partition B, McBSP #0
//--------------------------------------------------------------------
#define PCR0 (*(ioport unsigned int *)0x2812)//Pin Control Register, McBSP #0
//--------------------------------------------------------------------
#define RCERC_0 (*(ioport unsigned int *)0x2813)//Receive Channel Enable Register Partition C, McBSP #0
#define RCERD_0 (*(ioport unsigned int *)0x2814)//Receive Channel Enable Register Partition D, McBSP #0
#define XCERC_0 (*(ioport unsigned int *)0x2815)//Transmit Channel Enable Register Partition C, McBSP #0
#define XCERD_0 (*(ioport unsigned int *)0x2816)//Transmit Channel Enable Register Partition D, McBSP #0
//--------------------------------------------------------------------
#define RCERE_0 (*(ioport unsigned int *)0x2817)//Receive Channel Enable Register Partition E, McBSP #0
#define RCERF_0 (*(ioport unsigned int *)0x2818)//Receive Channel Enable Register Partition F, McBSP #0
#define XCERE_0 (*(ioport unsigned int *)0x2819)//Transmit Channel Enable Register Partition E, McBSP #0
#define XCERF_0 (*(ioport unsigned int *)0x281a)//Transmit Channel Enable Register Partition F, McBSP #0
//--------------------------------------------------------------------
#define RCERG_0 (*(ioport unsigned int *)0x281b)//Receive Channel Enable Register Partition G, McBSP #0
#define RCERH_0 (*(ioport unsigned int *)0x281c)//Receive Channel Enable Register Partition H, McBSP #0
#define XCERG_0 (*(ioport unsigned int *)0x281d)//Transmit Channel Enable Register Partition G, McBSP #0
#define XCERH_0 (*(ioport unsigned int *)0x281e)//Transmit Channel Enable Register Partition H, McBSP #0
//---------------Mcbsp1-----------------------------------------------
#define DRR2_1 (*(ioport unsigned int *)0x2c00)//Data Receive Register 2, McBSP #1
#define DRR1_1 (*(ioport unsigned int *)0x2c01)//Data Receive Register 1, McBSP #1
#define DXR2_1 (*(ioport unsigned int *)0x2c02)//Data Transmit Register 2, McBSP #1
#define DXR1_1 (*(ioport unsigned int *)0x2c03)//Data Transmit Register 1, McBSP #1
//--------------------------------------------------------------------
#define SPCR2_1 (*(ioport unsigned int *)0x2c04)//Serial Port Control Register 2, McBSP #1
#define SPCR1_1 (*(ioport unsigned int *)0x2c05)//Serial Port Control Register 1, McBSP #1
#define RCR2_1 (*(ioport unsigned int *)0x2c06)//Receive Control Register 2, McBSP #1
#define RCR1_1 (*(ioport unsigned int *)0x2c07)//Receive Control Register 1, McBSP #1
#define XCR2_1 (*(ioport unsigned int *)0x2c08)//Transmit Control Register 2, McBSP #1
#define XCR1_1 (*(ioport unsigned int *)0x2c09)//Transmit Control Register 1, McBSP #1
#define SRGR2_1 (*(ioport unsigned int *)0x2c0a)//Sample Rate Generator Register 2, McBSP #1
#define SRGR1_1 (*(ioport unsigned int *)0x2c0b)//Sample Rate Generator Register 1, McBSP #1
#define MCR2_1 (*(ioport unsigned int *)0x2c0c)//Multichannel Control Register 2, McBSP #1
#define MCR1_1 (*(ioport unsigned int *)0x2c0d)//Multichannel Control Register 1, McBSP #1
//--------------------------------------------------------------------
#define RCERA_1 (*(ioport unsigned int *)0x2c0e)//Receive Channel Enable Register Partition A, McBSP #1
#define RCERB_1 (*(ioport unsigned int *)0x2c0f)//Receive Channel Enable Register Partition B, McBSP #1
#define XCERA_1 (*(ioport unsigned int *)0x2c10)//Transmit Channel Enable Register Partition A, McBSP #1
#define XCERB_1 (*(ioport unsigned int *)0x2c11)//Transmit Channel Enable Register Partition B, McBSP #1
//--------------------------------------------------------------------
#define PCR1 (*(ioport unsigned int *)0x2c12)//Pin Control Register, McBSP #1
//--------------------------------------------------------------------
#define RCERC_1 (*(ioport unsigned int *)0x2c13)//Receive Channel Enable Register Partition C, McBSP #1
#define RCERD_1 (*(ioport unsigned int *)0x2c14)//Receive Channel Enable Register Partition D, McBSP #1
#define XCERC_1 (*(ioport unsigned int *)0x2c15)//Transmit Channel Enable Register Partition C, McBSP #1
#define XCERD_1 (*(ioport unsigned int *)0x2c16)//Transmit Channel Enable Register Partition D, McBSP #1
//--------------------------------------------------------------------
#define RCERE_1 (*(ioport unsigned int *)0x2c17)//Receive Channel Enable Register Partition E, McBSP #1
#define RCERF_1 (*(ioport unsigned int *)0x2c18)//Receive Channel Enable Register Partition F, McBSP #1
#define XCERE_1 (*(ioport unsigned int *)0x2c19)//Transmit Channel Enable Register Partition E, McBSP #1
#define XCERF_1 (*(ioport unsigned int *)0x2c1a)//Transmit Channel Enable Register Partition F, McBSP #1
//--------------------------------------------------------------------
#define RCERG_1 (*(ioport unsigned int *)0x2c1b)//Receive Channel Enable Register Partition G, McBSP #1
#define RCERH_1 (*(ioport unsigned int *)0x2c1c)//Receive Channel Enable Register Partition H, McBSP #1
#define XCERG_1 (*(ioport unsigned int *)0x2c1d)//Transmit Channel Enable Register Partition G, McBSP #1
#define XCERH_1 (*(ioport unsigned int *)0x2c1e)//Transmit Channel Enable Register Partition H, McBSP #1
//---------------Mcbsp2----------------------------------------------------
#define DRR2_2 (*(ioport unsigned int *)0x3000)//Data Receive Register 2, McBSP #2
#define DRR1_2 (*(ioport unsigned int *)0x3001)//Data Receive Register 1, McBSP #2
#define DXR2_2 (*(ioport unsigned int *)0x3002)//Data Transmit Register 2, McBSP #2
#define DXR1_2 (*(ioport unsigned int *)0x3003)//Data Transmit Register 1, McBSP #2
//--------------------------------------------------------------------
#define SPCR2_2 (*(ioport unsigned int *)0x3004)//Serial Port Control Register 2, McBSP #2
#define SPCR1_2 (*(ioport unsigned int *)0x3005)//Serial Port Control Register 1, McBSP #2
#define RCR2_2 (*(ioport unsigned int *)0x3006)//Receive Control Register 2, McBSP #2
#define RCR1_2 (*(ioport unsigned int *)0x3007)//Receive Control Register 1, McBSP #2
#define XCR2_2 (*(ioport unsigned int *)0x3008)//Transmit Control Register 2, McBSP #2
#define XCR1_2 (*(ioport unsigned int *)0x3009)//Transmit Control Register 1, McBSP #2
#define SRGR2_2 (*(ioport unsigned int *)0x300a)//Sample Rate Generator Register 2, McBSP #2
#define SRGR1_2 (*(ioport unsigned int *)0x300b)//Sample Rate Generator Register 1, McBSP #2
#define MCR2_2 (*(ioport unsigned int *)0x300c)//Multichannel Control Register 2, McBSP #2
#define MCR1_2 (*(ioport unsigned int *)0x300d)//Multichannel Control Register 1, McBSP #2
//--------------------------------------------------------------------
#define RCERA_2 (*(ioport unsigned int *)0x300e)//Receive Channel Enable Register Partition A, McBSP #2
#define RCERB_2 (*(ioport unsigned int *)0x300f)//Receive Channel Enable Register Partition B, McBSP #2
#define XCERA_2 (*(ioport unsigned int *)0x3010)//Transmit Channel Enable Register Partition A, McBSP #2
#define XCERB_2 (*(ioport unsigned int *)0x3011)//Transmit Channel Enable Register Partition B, McBSP #2
//--------------------------------------------------------------------
#define PCR2 (*(ioport unsigned int *)0x3012)//Pin Control Register, McBSP #2
//--------------------------------------------------------------------
#define RCERC_2 (*(ioport unsigned int *)0x3013)//Receive Channel Enable Register Partition C, McBSP #2
#define RCERD_2 (*(ioport unsigned int *)0x3014)//Receive Channel Enable Register Partition D, McBSP #2
#define XCERC_2 (*(ioport unsigned int *)0x3015)//Transmit Channel Enable Register Partition C, McBSP #2
#define XCERD_2 (*(ioport unsigned int *)0x3016)//Transmit Channel Enable Register Partition D, McBSP #2
//--------------------------------------------------------------------
#define RCERE_2 (*(ioport unsigned int *)0x3017)//Receive Channel Enable Register Partition E, McBSP #2
#define RCERF_2 (*(ioport unsigned int *)0x3018)//Receive Channel Enable Register Partition F, McBSP #2
#define XCERE_2 (*(ioport unsigned int *)0x3019)//Transmit Channel Enable Register Partition E, McBSP #2
#define XCERF_2 (*(ioport unsigned int *)0x301a)//Transmit Channel Enable Register Partition F, McBSP #2
//--------------------------------------------------------------------
#define RCERG_2 (*(ioport unsigned int *)0x301b)//Receive Channel Enable Register Partition G, McBSP #2
#define RCERH_2 (*(ioport unsigned int *)0x301c)//Receive Channel Enable Register Partition H, McBSP #2
#define XCERG_2 (*(ioport unsigned int *)0x301d)//Transmit Channel Enable Register Partition G, McBSP #2
#define XCERH_2 (*(ioport unsigned int *)0x301e)//Transmit Channel Enable Register Partition H, McBSP #2
//--------------------------------------------------------------------
//---------------------GPIO Registers---------------------------------
#define IODIR (*(ioport unsigned int *)0x3400)//General-purpose I/O Direction Register
#define IODATA (*(ioport unsigned int *)0x3401)//General-purpose I/O Data Register
#define AGPIOEN (*(ioport unsigned int *)0x4400)//Address/GPIO Enable Register
#define AGPIODIR (*(ioport unsigned int *)0x4401)//Address/GPIO Direction Register
#define AGPIODATA (*(ioport unsigned int *)0x4402)//Address/GPIO Data Register
#define EHPIGPIOEN (*(ioport unsigned int *)0x4403)//EHPI/GPIO Enable Register
#define EHPIGPIODIR (*(ioport unsigned int *)0x4404)//EHPI/GPIO Direction Register
#define EHPIGPIODATA (*(ioport unsigned int *)0x4405)//EHPI/GPIO Data Register
//--------------------------------------------------------------------
//---------------------Devicie IO Registers---------------------------
#define RevID (*(ioport unsigned int *)0x3803)//Silicon Revision Identification
//--------------------------------------------------------------------
//----------------------I2C MODE Registers----------------------------
#define I2CCOAR (*(ioport unsigned int *)0x3c00)//I2C Own Address Register
#define I2CIMR (*(ioport unsigned int *)0x3c01)//I2C Interrupt Mask Register
#define I2CSTR (*(ioport unsigned int *)0x3c02)//I2C Status Register
#define I2CCLKL (*(ioport unsigned int *)0x3c03)//I2C Clock Divider Low Register
#define I2CCLKH (*(ioport unsigned int *)0x3c04)//I2C Clock Divider High Register
#define I2CCNT (*(ioport unsigned int *)0x3c05)//I2C Data Count
#define I2CDRR (*(ioport unsigned int *)0x3c06)//I2C Data Receive Register
#define I2CSAR (*(ioport unsigned int *)0x3c07)//I2C Slave Address Register
#define I2CDXR (*(ioport unsigned int *)0x3c08)//I2C Data Transmit Register
#define I2CMDR (*(ioport unsigned int *)0x3c09)//I2C Mode Register
#define I2CIVR (*(ioport unsigned int *)0x3c0a)//I2C Interrupt Vector Register
//#define #3c0bh, //Reserved
#define I2CPSC (*(ioport unsigned int *)0x3c0c)//I2C Prescaler Register
//#define #3c0dh, //Reserved
//#define #3c0eh, //Reserved
#define I2CMDR2 (*(ioport unsigned int *)0x3c0f)//I2C Mode Register 2
//--------------------------------------------------------------------
//---------------------Watchdog Timer Registers-----------------------
#define WDTIM (*(ioport unsigned int *)0x4000)//WD Timer Counter Register
#define WDPRD (*(ioport unsigned int *)0x4001)//WD Timer Period Register
#define WDTCR (*(ioport unsigned int *)0x4002)//WD Timer Control Register
#define WDTCR2 (*(ioport unsigned int *)0x4003)//WD Timer Control Register 2
//--------------------------------------------------------------------
//--------------------------------------------------------------------
#define SD1 1 //默认为SD1=1
#ifdef SD1 //如果是SD1 ，设置寄存器为下面的地址
//--------------------------------------------------------------------
//--------------------MMC/SD1 Module Registers------------------------
#define MMCFCLK (*(ioport unsigned int *)0x4800)//MMC Function Clock Control Register
#define MMCCTL (*(ioport unsigned int *)0x4801)//MMC Control Register
#define MMCCLK (*(ioport unsigned int *)0x4802)//MMC Clock Control Register
#define MMCST0 (*(ioport unsigned int *)0x4803)//MMC Status Register 0
#define MMCST1 (*(ioport unsigned int *)0x4804)//MMC Status Register 1
#define MMCIE (*(ioport unsigned int *)0x4805)//MMC Interrupt Enable Register
#define MMCTOR (*(ioport unsigned int *)0x4806)//MMC Response Time-Out Register
#define MMCTOD (*(ioport unsigned int *)0x4807)//MMC Data Read Time-Out Register
#define MMCBLEN (*(ioport unsigned int *)0x4808)//MMC Block Length Register
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