📄 reg5509a.h
字号:
#define SDC1 (*(ioport unsigned int *)0x080f)//EMIF SDRAM Control Register 1
#define SDPER (*(ioport unsigned int *)0x0810)//EMIF SDRAM Period Register
#define SDCNT (*(ioport unsigned int *)0x0811)//EMIF SDRAM Counter Register
#define INIT (*(ioport unsigned int *)0x0812)//EMIF SDRAM Init Register
#define SDC2 (*(ioport unsigned int *)0x0813)//EMIF SDRAM Control Register 2
#define SDC3 (*(ioport unsigned int *)0x0814)//EMIF SDRAM Control Register 3
//--------------------------------------------------------------------
//------------------DMA Configuration Registers-----------------------
//--------------------------------------------------------------------
#define DMA_GCR (*(ioport unsigned int *)0x0e00)//DMA Global Control Register
#define DMA_GSCR (*(ioport unsigned int *)0x0e02)//DMA Software Compatibility Register
#define DMA_GTCR (*(ioport unsigned int *)0x0e03)//DMA Timeout Control Register
//------------------channal 0-----------------------------------------
#define DMA_CSDP0 (*(ioport unsigned int *)0x0c00)//DMA Channel 0 Source Destination
#define DMA_CCR0 (*(ioport unsigned int *)0x0c01)//DMA Channel 0 Control Register
#define DMA_CICR0 (*(ioport unsigned int *)0x0c02)//DMA Channel 0 Interrupt Control Register
#define DMA_CSR0 (*(ioport unsigned int *)0x0c03)//DMA Channel 0 Status Register
#define DMA_CSSA_L0 (*(ioport unsigned int *)0x0c04)//DMA Channel 0 Source Start Address Register
#define DMA_CSSA_U0 (*(ioport unsigned int *)0x0c05)//DMA Channel 0 Source Start Address Register
#define DMA_CDSA_L0 (*(ioport unsigned int *)0x0c06)//DMA Channel 0 Source Destination Address Register
#define DMA_CDSA_U0 (*(ioport unsigned int *)0x0c07)//DMA Channel 0 Source Destination Address Register
#define DMA_CEN0 (*(ioport unsigned int *)0x0c08)//DMA Channel 0 Element Number Register
#define DMA_CFN0 (*(ioport unsigned int *)0x0c09)//DMA Channel 0 Frame Number Register
#define DMA_CFI0 (*(ioport unsigned int *)0x0c0a)//DMA Channel 0 Frame Index Register/
#define DMA_CEI0 (*(ioport unsigned int *)0x0c0b)//DMA Channel 0 Element Index Register/
#define DMA_CSAC0 (*(ioport unsigned int *)0x0c0c)//DMA Channel 0 Source Address Counter
#define DMA_CDAC0 (*(ioport unsigned int *)0x0c0d)//DMA Channel 0 Destination Address Counter
#define DMA_CDEI0 (*(ioport unsigned int *)0x0c0e)//DMA Channel 0 Destination Element Index Register
#define DMA_CDFI0 (*(ioport unsigned int *)0x0c0f)//DMA Channel 0 Destination Frame Index Register
//-------------------channal 1----------------------------------------
#define DMA_CSDP1 (*(ioport unsigned int *)0x0c20)//DMA Channel 1 Source Destination
#define DMA_CCR1 (*(ioport unsigned int *)0x0c21)//DMA Channel 1 Control Register
#define DMA_CICR1 (*(ioport unsigned int *)0x0c22)//DMA Channel 1 Interrupt Control Register
#define DMA_CSR1 (*(ioport unsigned int *)0x0c23)//DMA Channel 1 Status Register
#define DMA_CSSA_L1 (*(ioport unsigned int *)0x0c24)//DMA Channel 1 Source Start Address Register
#define DMA_CSSA_U1 (*(ioport unsigned int *)0x0c25)//DMA Channel 1 Source Start Address Register
#define DMA_CDSA_L1 (*(ioport unsigned int *)0x0c26)//DMA Channel 1 Source Destination Address Register
#define DMA_CDSA_U1 (*(ioport unsigned int *)0x0c27)//DMA Channel 1 Source Destination Address Register
#define DMA_CEN1 (*(ioport unsigned int *)0x0c28)//DMA Channel 1 Element Number Register
#define DMA_CFN1 (*(ioport unsigned int *)0x0c29)//DMA Channel 1 Frame Number Register
#define DMA_CFI1 (*(ioport unsigned int *)0x0c2a)//DMA Channel 1 Frame Index Register/
#define DMA_CEI1 (*(ioport unsigned int *)0x0c2b)//DMA Channel 1 Element Index Register/
#define DMA_CSAC1 (*(ioport unsigned int *)0x0c2c)//DMA Channel 1 Source Address Counter
#define DMA_CDAC1 (*(ioport unsigned int *)0x0c2d)//DMA Channel 1 Destination Address Counter
#define DMA_CDEI1 (*(ioport unsigned int *)0x0c2e)//DMA Channel 1 Destination Element Index Register
#define DMA_CDFI1 (*(ioport unsigned int *)0x0c2f)//DMA Channel 1 Destination Frame Index Register
//-----------------------------channal 2---------------------------------------
#define DMA_CSDP2 (*(ioport unsigned int *)0x0c40)//DMA Channel 2 Source Destination
#define DMA_CCR2 (*(ioport unsigned int *)0x0c41)//DMA Channel 2 Control Register
#define DMA_CICR2 (*(ioport unsigned int *)0x0c42)//DMA Channel 2 Interrupt Control Register
#define DMA_CSR2 (*(ioport unsigned int *)0x0c43)//DMA Channel 2 Status Register
#define DMA_CSSA_L2 (*(ioport unsigned int *)0x0c44)//DMA Channel 2 Source Start Address Register
#define DMA_CSSA_U2 (*(ioport unsigned int *)0x0c45)//DMA Channel 2 Source Start Address Register
#define DMA_CDSA_L2 (*(ioport unsigned int *)0x0c46)//DMA Channel 2 Source Destination Address Register
#define DMA_CDSA_U2 (*(ioport unsigned int *)0x0c47)//DMA Channel 2 Source Destination Address Register
#define DMA_CEN2 (*(ioport unsigned int *)0x0c48)//DMA Channel 2 Element Number Register
#define DMA_CFN2 (*(ioport unsigned int *)0x0c49)//DMA Channel 2 Frame Number Register
#define DMA_CFI2 (*(ioport unsigned int *)0x0c4a)//DMA Channel 2 Frame Index Register/
#define DMA_CEI2 (*(ioport unsigned int *)0x0c4b)//DMA Channel 2 Element Index Register/
#define DMA_CSAC2 (*(ioport unsigned int *)0x0c4c)//DMA Channel 2 Source Address Counter
#define DMA_CDAC2 (*(ioport unsigned int *)0x0c4d)//DMA Channel 2 Destination Address Counter
#define DMA_CDEI2 (*(ioport unsigned int *)0x0c4e)//DMA Channel 2 Destination Element Index Register
#define DMA_CDFI2 (*(ioport unsigned int *)0x0c4f)//DMA Channel 2 Destination Frame Index Register
//-----------channal 3---------
#define DMA_CSDP3 (*(ioport unsigned int *)0x0c60)//DMA Channel 3 Source Destination
#define DMA_CCR3 (*(ioport unsigned int *)0x0c61)//DMA Channel 3 Control Register
#define DMA_CICR3 (*(ioport unsigned int *)0x0c62)//DMA Channel 3 Interrupt Control Register
#define DMA_CSR3 (*(ioport unsigned int *)0x0c63)//DMA Channel 3 Status Register
#define DMA_CSSA_L3 (*(ioport unsigned int *)0x0c64)//DMA Channel 3 Source Start Address Register
#define DMA_CSSA_U3 (*(ioport unsigned int *)0x0c65)//DMA Channel 3 Source Start Address Register
#define DMA_CDSA_L3 (*(ioport unsigned int *)0x0c66)//DMA Channel 3 Source Destination Address Register
#define DMA_CDSA_U3 (*(ioport unsigned int *)0x0c67)//DMA Channel 3 Source Destination Address Register
#define DMA_CEN3 (*(ioport unsigned int *)0x0c68)//DMA Channel 3 Element Number Register
#define DMA_CFN3 (*(ioport unsigned int *)0x0c69)//DMA Channel 3 Frame Number Register
#define DMA_CFI3 (*(ioport unsigned int *)0x0c6a)//DMA Channel 3 Frame Index Register/
#define DMA_CEI3 (*(ioport unsigned int *)0x0c6b)//DMA Channel 3 Element Index Register/
#define DMA_CSAC3 (*(ioport unsigned int *)0x0c6c)//DMA Channel 3 Source Address Counter
#define DMA_CDAC3 (*(ioport unsigned int *)0x0c6d)//DMA Channel 3 Destination Address Counter
#define DMA_CDEI3 (*(ioport unsigned int *)0x0c6e)//DMA Channel 3 Destination Element Index Register
#define DMA_CDFI3 (*(ioport unsigned int *)0x0c6f)//DMA Channel 3 Destination Frame Index Register
//----------channal 4---------
#define DMA_CSDP4 (*(ioport unsigned int *)0x0c80)//DMA Channel 4 Source Destination
#define DMA_CCR4 (*(ioport unsigned int *)0x0c81)//DMA Channel 4 Control Register
#define DMA_CICR4 (*(ioport unsigned int *)0x0c82)//DMA Channel 4 Interrupt Control Register
#define DMA_CSR4 (*(ioport unsigned int *)0x0c83)//DMA Channel 4 Status Register
#define DMA_CSSA_L4 (*(ioport unsigned int *)0x0c84)//DMA Channel 4 Source Start Address Register
#define DMA_CSSA_U4 (*(ioport unsigned int *)0x0c85)//DMA Channel 4 Source Start Address Register
#define DMA_CDSA_L4 (*(ioport unsigned int *)0x0c86)//DMA Channel 4 Source Destination Address Register
#define DMA_CDSA_U4 (*(ioport unsigned int *)0x0c87)//DMA Channel 4 Source Destination Address Register
#define DMA_CEN4 (*(ioport unsigned int *)0x0c88)//DMA Channel 4 Element Number Register
#define DMA_CFN4 (*(ioport unsigned int *)0x0c89)//DMA Channel 4 Frame Number Register
#define DMA_CFI4 (*(ioport unsigned int *)0x0c8a)//DMA Channel 4 Frame Index Register/
#define DMA_CEI4 (*(ioport unsigned int *)0x0c8b)//DMA Channel 4 Element Index Register/
#define DMA_CSAC4 (*(ioport unsigned int *)0x0c8c)//DMA Channel 4 Source Address Counter
#define DMA_CDAC4 (*(ioport unsigned int *)0x0c8d)//DMA Channel 4 Destination Address Counter
#define DMA_CDEI4 (*(ioport unsigned int *)0x0c8e)//DMA Channel 4 Destination Element Index Register
#define DMA_CDFI4 (*(ioport unsigned int *)0x0c8f)//DMA Channel 4 Destination Frame Index Register
//---------channal 5----------
#define DMA_CSDP5 (*(ioport unsigned int *)0x0ca0)//DMA Channel 5 Source Destination
#define DMA_CCR5 (*(ioport unsigned int *)0x0ca1)//DMA Channel 5 Control Register
#define DMA_CICR5 (*(ioport unsigned int *)0x0ca2)//DMA Channel 5 Interrupt Control Register
#define DMA_CSR5 (*(ioport unsigned int *)0x0ca3)//DMA Channel 5 Status Register
#define DMA_CSSA_L5 (*(ioport unsigned int *)0x0ca4)//DMA Channel 5 Source Start Address Register
#define DMA_CSSA_U5 (*(ioport unsigned int *)0x0ca5)//DMA Channel 5 Source Start Address Register
#define DMA_CDSA_L5 (*(ioport unsigned int *)0x0ca6)//DMA Channel 5 Source Destination Address Register
#define DMA_CDSA_U5 (*(ioport unsigned int *)0x0ca7)//DMA Channel 5 Source Destination Address Register
#define DMA_CEN5 (*(ioport unsigned int *)0x0ca8)//DMA Channel 5 Element Number Register
#define DMA_CFN5 (*(ioport unsigned int *)0x0ca9)//DMA Channel 5 Frame Number Register
#define DMA_CFI5 (*(ioport unsigned int *)0x0caa)//DMA Channel 5 Frame Index Register/
#define DMA_CEI5 (*(ioport unsigned int *)0x0cab)//DMA Channel 5 Element Index Register/
#define DMA_CSAC5 (*(ioport unsigned int *)0x0cac)//DMA Channel 5 Source Address Counter
#define DMA_CDAC5 (*(ioport unsigned int *)0x0cad)//DMA Channel 5 Destination Address Counter
#define DMA_CDEI5 (*(ioport unsigned int *)0x0cae)//DMA Channel 5 Destination Element Index Register
#define DMA_CDFI5 (*(ioport unsigned int *)0x0caf)//DMA Channel 5 Destination Frame Index Register
//--------------------------------------------------------------------
//-------------Real-Time Clock Registers------------------------------
#define RTCSEC (*(ioport unsigned int *)0x1800)//Seconds Register
#define RTCSECA (*(ioport unsigned int *)0x1801)//Seconds Alarm Register
#define RTCMIN (*(ioport unsigned int *)0x1802)//Minutes Register
#define RTCMINA (*(ioport unsigned int *)0x1803)//Minutes Alarm Register
#define RTCHOUR (*(ioport unsigned int *)0x1804)//Hours Register
#define RTCHOURA (*(ioport unsigned int *)0x1805)//Hours Alarm Register
#define RTCDAYW (*(ioport unsigned int *)0x1806)//Day of the Week Register
#define RTCDAYM (*(ioport unsigned int *)0x1807)//Day of the Month (date) Register
#define RTCMONTH (*(ioport unsigned int *)0x1808)//Month Register
#define RTCYEAR (*(ioport unsigned int *)0x1809)//Year Register
#define RTCPINTR (*(ioport unsigned int *)0x180a)//Periodic Interrupt Selection Register
#define RTCINTEN (*(ioport unsigned int *)0x180b)//Interrupt Enable Register
#define RTCINTFL (*(ioport unsigned int *)0x180c)//Interrupt Flag Register
//--------------------------------------------------------------------
//-------------- 0x180D~0x1BFF Reserved---------------------------
//--------------------------------------------------------------------
//-------------- Clock Generator-----------------------------------
#define CLKMD (*(ioport unsigned int *)0x1c00)//Clock Mode Register
#define USBDPLL (*(ioport unsigned int *)0x1e00)//USB DPLL Control Register
#define USBPLLSEL (*(ioport unsigned int *)0x1e80)//USB PLL Selection Register
#define USBAPLL (*(ioport unsigned int *)0x1f00)//USB APLL Control Register
//--------------------------------------------------------------------
//------------------Timer --------------------------------------------
//------------------Timer0---------------------------------------------
#define TIM0 (*(ioport unsigned int *)0x1000)//Timer Count Register, Timer #0
#define PRD0 (*(ioport unsigned int *)0x1001)//Period Register, Timer #0
#define TCR0 (*(ioport unsigned int *)0x1002)//Timer Control Register, Timer #0
#define PRSC0 (*(ioport unsigned int *)0x1003)//Timer Prescaler Register, Timer #0
//------------------Timer1---------------------------------------------
#define TIM1 (*(ioport unsigned int *)0x2400)//Timer Count Register, Timer #1
#define PRD1 (*(ioport unsigned int *)0x2401)//Period Register, Timer #1
#define TCR1 (*(ioport unsigned int *)0x2401)//Timer Control Register, Timer #1
#define PRSC1 (*(ioport unsigned int *)0x2403)//Timer Prescaler Register, Timer #1
//--------------------------------------------------------------------
//-------------------Mcbsp0-------------------------------------------
#define DRR2_0 (*(ioport unsigned int *)0x2800)//Data Receive Register 2, McBSP #0
#define DRR1_0 (*(ioport unsigned int *)0x2801)//Data Receive Register 1, McBSP #0
#define DXR2_0 (*(ioport unsigned int *)0x2802)//Data Transmit Register 2, McBSP #0
#define DXR1_0 (*(ioport unsigned int *)0x2803)//Data Transmit Register 1, McBSP #0
//--------------------------------------------------------------------
#define SPCR2_0 (*(ioport unsigned int *)0x2804)//Serial Port Control Register 2, McBSP #0
#define SPCR1_0 (*(ioport unsigned int *)0x2805)//Serial Port Control Register 1, McBSP #0
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -