📄 phase1.mdl
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ExtModeStaticAlloc off
ExtModeTesting off
ExtModeStaticAllocSize 1000000
ExtModeTransport 0
ExtModeMexFile "ext_comm"
RTWCAPISignals off
RTWCAPIParams off
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}
PropName "Components"
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hdlcoderui.hdlcc {
$ObjectID 11
Description "HDL Coder custom configuration component"
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Name "HDL Coder"
Array {
Type "Cell"
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Cell ""
PropName "HDLConfigFile"
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HDLCActiveTab "0"
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PropName "Components"
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Name "Configuration"
CurrentDlgPage "Solver"
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Block {
BlockType Abs
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Block {
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VectorParams1D on
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OutDataTypeMode "Inherit from 'Constant value'"
OutDataType "sfix(16)"
ConRadixGroup "Use specified scaling"
OutScaling "2^0"
SampleTime "inf"
FramePeriod "inf"
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Block {
BlockType DiscretePulseGenerator
PulseType "Sample based"
TimeSource "Use simulation time"
Amplitude "1"
Period "2"
PulseWidth "1"
PhaseDelay "0"
SampleTime "1"
VectorParams1D on
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Block {
BlockType FrameConversion
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Block {
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Expr "sin(u[1])"
SampleTime "-1"
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ParameterDataTypeMode "Same as input"
ParameterDataType "sfix(16)"
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ParameterScaling "2^0"
OutDataTypeMode "Same as input"
OutDataType "sfix(16)"
OutScaling "2^0"
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RndMeth "Floor"
SaturateOnIntegerOverflow on
SampleTime "-1"
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BlockType InitialCondition
Value "1"
SampleTime "-1"
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Block {
BlockType Inport
Port "1"
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BusObject "BusObject"
BusOutputAsStruct off
PortDimensions "-1"
SampleTime "-1"
DataType "auto"
OutDataType "sfix(16)"
OutScaling "2^0"
SignalType "auto"
SamplingMode "auto"
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LatchByCopyingInsideSignal off
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LogicDataType "uint(8)"
SampleTime "-1"
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Block {
BlockType Math
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OutputSignalType "auto"
SampleTime "-1"
OutDataTypeMode "Same as first input"
OutDataType "sfix(16)"
OutScaling "2^0"
LockScale off
RndMeth "Floor"
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Block {
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BusObject "BusObject"
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PortDimensions "-1"
SampleTime "-1"
DataType "auto"
OutDataType "sfix(16)"
OutScaling "2^0"
SignalType "auto"
SamplingMode "auto"
OutputWhenDisabled "held"
InitialOutput "[]"
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BlockType Reference
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Block {
BlockType RelationalOperator
Operator ">="
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LogicOutDataTypeMode "Logical (see Configuration Parameters: Optimiza"
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LogicDataType "uint(8)"
ZeroCross on
SampleTime "-1"
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Block {
BlockType Reshape
OutputDimensionality "1-D array"
OutputDimensions "[1,1]"
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Block {
BlockType Scope
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TickLabels "OneTimeTick"
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TimeRange "auto"
YMin "-5"
YMax "5"
SaveToWorkspace off
SaveName "ScopeData"
LimitDataPoints on
MaxDataPoints "5000"
Decimation "1"
SampleInput off
SampleTime "-1"
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Block {
BlockType "S-Function"
FunctionName "system"
SFunctionModules "''"
PortCounts "[]"
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Block {
BlockType SubSystem
ShowPortLabels "FromPortIcon"
Permissions "ReadWrite"
PermitHierarchicalResolution "All"
TreatAsAtomicUnit off
SystemSampleTime "-1"
RTWFcnNameOpts "Auto"
RTWFileNameOpts "Auto"
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
SimViewingDevice off
DataTypeOverride "UseLocalSettings"
MinMaxOverflowLogging "UseLocalSettings"
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Block {
BlockType Sum
IconShape "rectangular"
Inputs "++"
CollapseMode "All dimensions"
CollapseDim "1"
InputSameDT on
OutDataTypeMode "Same as first input"
OutDataType "sfix(16)"
OutScaling "2^0"
LockScale off
RndMeth "Floor"
SaturateOnIntegerOverflow on
SampleTime "-1"
}
Block {
BlockType Terminator
}
}
AnnotationDefaults {
HorizontalAlignment "center"
VerticalAlignment "middle"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
FontName "Arial"
FontSize 10
FontWeight "normal"
FontAngle "normal"
UseDisplayTextAsClickCallback off
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LineDefaults {
FontName "Arial"
FontSize 9
FontWeight "normal"
FontAngle "normal"
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System {
Name "phase1"
Location [2, 78, 1278, 749]
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ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
TiledPaperMargins [0.500000, 0.500000, 0.500000, 0.500000]
TiledPageScale 1
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ZoomFactor "100"
ReportName "simulink-default.rpt"
Block {
BlockType Reference
Name "Frequency Divider"
Ports [1, 1]
Position [400, 116, 500, 164]
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FontName "Arial"
SourceBlock "commblksprivate/Frequency Divider"
SourceType "Frequency Divider"
ShowPortLabels "FromPortIcon"
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
n "synM"
}
Block {
BlockType Reference
Name "Frequency Divider1"
Ports [1, 1]
Position [660, 251, 765, 299]
Orientation "left"
ShowName off
FontName "Arial"
SourceBlock "commblksprivate/Frequency Divider"
SourceType "Frequency Divider"
ShowPortLabels "FromPortIcon"
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
n "synN"
}
Block {
BlockType Logic
Name "Phase\nDetector"
Ports [2, 1]
Position [570, 132, 600, 163]
FontName "Helvetica"
Operator "XOR"
OutDataTypeMode "Boolean"
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Block {
BlockType DiscretePulseGenerator
Name "Pulse\nGenerator"
Ports [0, 1]
Position [305, 125, 335, 155]
FontName "Helvetica"
PulseType "Time based"
Period "1/synFr"
PulseWidth "50"
}
Block {
BlockType Scope
Name "Synthesized\nSignal"
Ports [1]
Position [835, 134, 865, 166]
FontName "Helvetica"
Floating off
Location [350, 59, 674, 300]
Open off
NumInputPorts "1"
ZoomMode "xonly"
List {
ListType AxesTitles
axes1 "%<SignalLabel>"
}
TimeRange "5e-008"
YMin "-1"
YMax "2"
DataFormat "StructureWithTime"
MaxDataPoints "50000"
SampleTime "0"
}
Block {
BlockType Reference
Name "Voltage-Controlled\nOscillator"
Ports [1, 1]
Position [675, 128, 740, 172]
ShowName off
FontName "Helvetica"
SourceBlock "commsynccomp2/Continuous-Time\nVCO"
SourceType "Continuous-Time VCO"
ShowPortLabels "FromPortIcon"
SystemSampleTime "-1"
FunctionWithSeparateData off
RTWMemSecFuncInitTerm "Inherit from model"
RTWMemSecFuncExecute "Inherit from model"
RTWMemSecDataConstants "Inherit from model"
RTWMemSecDataInternal "Inherit from model"
RTWMemSecDataParameters "Inherit from model"
Ac "1"
Fc "synFq"
Kc "synSen"
Ph "0"
}
Line {
SrcBlock "Phase\nDetector"
SrcPort 1
DstBlock "Voltage-Controlled\nOscillator"
DstPort 1
}
Line {
SrcBlock "Voltage-Controlled\nOscillator"
SrcPort 1
Points [50, 0]
Branch {
DstBlock "Synthesized\nSignal"
DstPort 1
}
Branch {
Points [0, 125]
DstBlock "Frequency Divider1"
DstPort 1
}
}
Line {
SrcBlock "Pulse\nGenerator"
SrcPort 1
DstBlock "Frequency Divider"
DstPort 1
}
Line {
SrcBlock "Frequency Divider"
SrcPort 1
DstBlock "Phase\nDetector"
DstPort 1
}
Line {
SrcBlock "Frequency Divider1"
SrcPort 1
Points [-110, 0; 0, -120]
DstBlock "Phase\nDetector"
DstPort 2
}
}
}
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