ide.c

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/* $Id: ide.c,v 1.19 2001/05/09 12:53:16 johana Exp $
 *
 * Etrax specific IDE functions, like init and PIO-mode setting etc.
 * Almost the entire ide.c is used for the rest of the Etrax ATA driver.
 * Copyright (c) 2000, 2001 Axis Communications AB 
 *
 * Authors:    Bjorn Wesen        (initial version)
 *             Mikael Starvik     (pio setup stuff)
 *
 * $Log: ide.c,v $
 * Revision 1.19  2001/05/09 12:53:16  johana
 * Added #include <asm/dma.h>
 *
 * Revision 1.18  2001/05/09 12:37:00  johana
 * Use DMA_NBR macros from dma.h.
 *
 * Revision 1.17  2001/04/23 13:36:30  matsfg
 * Changed CONFIG_IDE_DELAY to CONFIG_ETRAX_IDE_DELAY
 *
 * Revision 1.16  2001/04/05 08:30:07  matsfg
 * Corrected cse1 and csp0 reset.
 *
 * Revision 1.15  2001/04/04 14:34:06  bjornw
 * Re-instated code that mysteriously disappeared during review updates.
 *
 * Revision 1.14  2001/04/04 13:45:12  matsfg
 * Calls REG_SHADOW_SET for cse1 reset so only the resetbit is affected
 *
 * Revision 1.13  2001/04/04 13:26:40  matsfg
 * memmapping is done in init.c
 *
 * Revision 1.12  2001/04/04 11:37:56  markusl
 * Updated according to review remarks
 *
 * Revision 1.11  2001/03/29 12:49:14  matsfg
 * Changed check for ata_tot_size from >= to >.
 * Sets sw_len to 0 if size is exactly 65536.
 *
 * Revision 1.10  2001/03/16 09:39:30  matsfg
 * Support for reset on port CSP0
 *
 * Revision 1.9  2001/03/01 13:11:18  bjornw
 * 100 -> HZ
 *
 * Revision 1.8  2001/03/01 09:32:56  matsfg
 * Moved IDE delay to a CONFIG-parameter instead
 *
 * Revision 1.7  2001/02/23 13:46:38  bjornw
 * Spellling check
 *
 * Revision 1.6  2001/02/22 15:44:30  bjornw
 * * Use ioremap when mapping the CSE1 memory-mapped reset-line for LX v2
 * * sw_len for a 65536 descriptor is 0, not 65536
 * * Express concern for G27 reset code
 *
 * Revision 1.5  2001/02/16 07:35:38  matsfg
 * Now handles DMA request blocks between 64k and 128k by split into two descriptors.
 *
 * Revision 1.4  2001/01/10 21:14:32  bjornw
 * Initialize hwif->ideproc, for the new way of handling ide_xxx_data
 *
 * Revision 1.3  2000/12/01 17:48:18  bjornw
 * - atapi_output_bytes now uses DMA
 * - dma_active check removed - the kernel does proper serializing and it had
 *   a race-condition anyway
 * - ide_build_dmatable had a nameclash
 * - re-added the RESET_DMA thingys because sometimes the interface can get
 *   stuck apparently
 * - added ide_release_dma
 *
 * Revision 1.2  2000/11/29 17:31:29  bjornw
 * 2.4 port
 *
 * - The "register addresses" stored in the hwif are now 32-bit fields that
 *   don't need to be shifted into correct positions in R_ATA_CTRL_DATA
 * - PIO-mode detection temporarily disabled since ide-modes.c is not compiled
 * - All DMA uses virt_to_phys conversions for DMA buffers and descriptor ptrs
 * - Probably correct ide_dma_begin semantics in dmaproc now for ATAPI devices
 * - Removed RESET_DMA when starting a new transfer - why was this necessary ?
 * - Indentation fix
 *
 *
 */

/* Regarding DMA: 
 *
 * There are two forms of DMA - "DMA handshaking" between the interface and the drive,
 * and DMA between the memory and the interface. We can ALWAYS use the latter, since it's
 * something built-in in the Etrax. However only some drives support the DMA-mode handshaking
 * on the ATA-bus. The normal PC driver and Triton interface disables memory-if DMA when the
 * device can't do DMA handshaking for some stupid reason. We don't need to do that.
 */ 

#undef REALLY_SLOW_IO           /* most systems can safely undef this */

#include <linux/config.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/timer.h>
#include <linux/mm.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/blkdev.h>
#include <linux/hdreg.h>
#include <linux/ide.h>
#include <linux/init.h>

#include <asm/io.h>
#include <asm/svinto.h>
#include <asm/dma.h>

/* number of Etrax DMA descriptors */
#define MAX_DMA_DESCRS 64

#ifdef CONFIG_ETRAX_IDE_CSE1_16_RESET
/* address where the memory-mapped IDE reset bit lives, if used */
static volatile unsigned long *reset_addr;
#endif

#define LOWDB(x)
#define D(x) 

void OUT_BYTE(unsigned char data, ide_ioreg_t reg) {
	LOWDB(printk("ob: data 0x%x, reg 0x%x\n", data, reg));
	while(*R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, busy)); /* wait for busy flag */
	*R_ATA_CTRL_DATA = reg | data; /* write data to the drive's register */
	while(!(*R_ATA_STATUS_DATA &
		IO_MASK(R_ATA_STATUS_DATA, tr_rdy))); /* wait for transmitter ready */
}

unsigned char IN_BYTE(ide_ioreg_t reg) {
	int status;
	while(*R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, busy)); /* wait for busy flag */
	*R_ATA_CTRL_DATA = reg | IO_STATE(R_ATA_CTRL_DATA, rw, read); /* read data */ 
	while(!((status = *R_ATA_STATUS_DATA) &
		IO_MASK(R_ATA_STATUS_DATA, dav))); /* wait for available */
	LOWDB(printk("inb: 0x%x from reg 0x%x\n", status & 0xff, reg));
	return (unsigned char)status; /* data was in the lower 16 bits in the status reg */
}

/* PIO timing (in R_ATA_CONFIG)
 *
 *                        _____________________________
 * ADDRESS :     ________/
 *
 *                            _______________
 * DIOR    :     ____________/               \__________
 *
 *                               _______________
 * DATA    :     XXXXXXXXXXXXXXXX_______________XXXXXXXX
 *
 *
 * DIOR is unbuffered while address and data is buffered.
 * This creates two problems:
 * 1. The DIOR pulse is to early (because it is unbuffered)
 * 2. The rise time of DIOR is long
 *
 * There are at least three different plausible solutions
 * 1. Use a pad capable of larger currents in Etrax
 * 2. Use an external buffer
 * 3. Make the strobe pulse longer
 *
 * Some of the strobe timings below are modified to compensate
 * for this. This implies a slight performance decrease.
 *
 * THIS SHOULD NEVER BE CHANGED!
 *
 * TODO: Is this true for the latest LX boards still ?
 */

#define ATA_DMA2_STROBE  4 
#define ATA_DMA2_HOLD    0
#define ATA_DMA1_STROBE  4 
#define ATA_DMA1_HOLD    1
#define ATA_DMA0_STROBE 12 
#define ATA_DMA0_HOLD    9
#define ATA_PIO4_SETUP   1
#define ATA_PIO4_STROBE  5
#define ATA_PIO4_HOLD    0
#define ATA_PIO3_SETUP   1
#define ATA_PIO3_STROBE  5
#define ATA_PIO3_HOLD    1
#define ATA_PIO2_SETUP   1
#define ATA_PIO2_STROBE  6
#define ATA_PIO2_HOLD    2
#define ATA_PIO1_SETUP   2
#define ATA_PIO1_STROBE 11
#define ATA_PIO1_HOLD    4
#define ATA_PIO0_SETUP   4
#define ATA_PIO0_STROBE 19
#define ATA_PIO0_HOLD    4

static int e100_dmaproc (ide_dma_action_t func, ide_drive_t *drive);
static void e100_ideproc (ide_ide_action_t func, ide_drive_t *drive,
			  void *buffer, unsigned int length);

/*
 * good_dma_drives() lists the model names (from "hdparm -i")
 * of drives which do not support mword2 DMA but which are
 * known to work fine with this interface under Linux.
 */

const char *good_dma_drives[] = {"Micropolis 2112A",
				 "CONNER CTMA 4000",
				 "CONNER CTT8000-A",
				 NULL};

static void tune_e100_ide(ide_drive_t *drive, byte pio)
{
	unsigned long flags;
	
	pio = 4;
	/* pio = ide_get_best_pio_mode(drive, pio, 4, NULL); */
	
	save_flags(flags);
	cli();

	/* set pio mode! */
  	 
	switch(pio) {
		case 0:
			*R_ATA_CONFIG = ( IO_FIELD( R_ATA_CONFIG, enable,     1 ) |
					  IO_FIELD( R_ATA_CONFIG, dma_strobe, ATA_DMA2_STROBE ) |
					  IO_FIELD( R_ATA_CONFIG, dma_hold,   ATA_DMA2_HOLD ) |
					  IO_FIELD( R_ATA_CONFIG, pio_setup,  ATA_PIO0_SETUP ) |
					  IO_FIELD( R_ATA_CONFIG, pio_strobe, ATA_PIO0_STROBE ) |
					  IO_FIELD( R_ATA_CONFIG, pio_hold,   ATA_PIO0_HOLD ) );
			break;
		case 1:
			*R_ATA_CONFIG = ( IO_FIELD( R_ATA_CONFIG, enable,     1 ) |
					  IO_FIELD( R_ATA_CONFIG, dma_strobe, ATA_DMA2_STROBE ) |
					  IO_FIELD( R_ATA_CONFIG, dma_hold,   ATA_DMA2_HOLD ) |
					  IO_FIELD( R_ATA_CONFIG, pio_setup,  ATA_PIO1_SETUP ) |
					  IO_FIELD( R_ATA_CONFIG, pio_strobe, ATA_PIO1_STROBE ) |
					  IO_FIELD( R_ATA_CONFIG, pio_hold,   ATA_PIO1_HOLD ) );
			break;
		case 2:
			*R_ATA_CONFIG = ( IO_FIELD( R_ATA_CONFIG, enable,     1 ) |
					  IO_FIELD( R_ATA_CONFIG, dma_strobe, ATA_DMA2_STROBE ) |
					  IO_FIELD( R_ATA_CONFIG, dma_hold,   ATA_DMA2_HOLD ) |
					  IO_FIELD( R_ATA_CONFIG, pio_setup,  ATA_PIO2_SETUP ) |
					  IO_FIELD( R_ATA_CONFIG, pio_strobe, ATA_PIO2_STROBE ) |
					  IO_FIELD( R_ATA_CONFIG, pio_hold,   ATA_PIO2_HOLD ) );
			break;
		case 3:
			*R_ATA_CONFIG = ( IO_FIELD( R_ATA_CONFIG, enable,     1 ) |
					  IO_FIELD( R_ATA_CONFIG, dma_strobe, ATA_DMA2_STROBE ) |
					  IO_FIELD( R_ATA_CONFIG, dma_hold,   ATA_DMA2_HOLD ) |
					  IO_FIELD( R_ATA_CONFIG, pio_setup,  ATA_PIO3_SETUP ) |
					  IO_FIELD( R_ATA_CONFIG, pio_strobe, ATA_PIO3_STROBE ) |
					  IO_FIELD( R_ATA_CONFIG, pio_hold,   ATA_PIO3_HOLD ) );
			break;
		case 4:
			*R_ATA_CONFIG = ( IO_FIELD( R_ATA_CONFIG, enable,     1 ) |
					  IO_FIELD( R_ATA_CONFIG, dma_strobe, ATA_DMA2_STROBE ) |
					  IO_FIELD( R_ATA_CONFIG, dma_hold,   ATA_DMA2_HOLD ) |
					  IO_FIELD( R_ATA_CONFIG, pio_setup,  ATA_PIO4_SETUP ) |
					  IO_FIELD( R_ATA_CONFIG, pio_strobe, ATA_PIO4_STROBE ) |
					  IO_FIELD( R_ATA_CONFIG, pio_hold,   ATA_PIO4_HOLD ) );
			break;
	}
	restore_flags(flags);
}

void __init 
init_e100_ide (void)
{
	volatile unsigned int dummy;
	int h;

	printk("ide: ETRAX 100LX built-in ATA DMA controller\n");

	/* first fill in some stuff in the ide_hwifs fields */
	
	for(h = 0; h < MAX_HWIFS; h++) {
		ide_hwif_t *hwif = &ide_hwifs[h];
		hwif->chipset = ide_etrax100;
		hwif->tuneproc = &tune_e100_ide;
		hwif->dmaproc = &e100_dmaproc;
		hwif->ideproc = &e100_ideproc;
	}
	/* actually reset and configure the etrax100 ide/ata interface */

	/* This is mystifying; why is not G27 SET anywhere ? It's just reset here twice. */

	/* de-assert bus-reset */
#ifdef CONFIG_ETRAX_IDE_PB7_RESET  
	port_pb_dir_shadow = port_pb_dir_shadow | 
		IO_STATE(R_PORT_PB_DIR, dir7, output);
	*R_PORT_PB_DIR = port_pb_dir_shadow;
	REG_SHADOW_SET(R_PORT_PB_DATA, port_pb_data_shadow, 7, 1);
#endif
#ifdef CONFIG_ETRAX_IDE_G27_RESET
	*R_PORT_G_DATA = 0;
#endif 

	*R_ATA_CTRL_DATA = 0;
	*R_ATA_TRANSFER_CNT = 0;
	*R_ATA_CONFIG = 0;

	genconfig_shadow = (genconfig_shadow & 
			    ~IO_MASK(R_GEN_CONFIG, dma2) &
			    ~IO_MASK(R_GEN_CONFIG, dma3) &
			    ~IO_MASK(R_GEN_CONFIG, ata)) | 
		( IO_STATE( R_GEN_CONFIG, dma3, ata    ) |
		  IO_STATE( R_GEN_CONFIG, dma2, ata    ) |
		  IO_STATE( R_GEN_CONFIG, ata,  select ) );

	*R_GEN_CONFIG = genconfig_shadow;

#ifdef CONFIG_ETRAX_IDE_CSE1_16_RESET
        init_ioremap();
        REG_SHADOW_SET(port_cse1_addr, port_cse1_shadow, 16, 0);
#endif

#ifdef CONFIG_ETRAX_IDE_CSP0_8_RESET
        init_ioremap();
        REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, 8, 0);
#endif

	/* wait some */
	udelay(25);

#ifdef CONFIG_ETRAX_IDE_CSE1_16_RESET
	REG_SHADOW_SET(port_cse1_addr, port_cse1_shadow, 16, 1);
#endif
#ifdef CONFIG_ETRAX_IDE_CSP0_8_RESET
	REG_SHADOW_SET(port_csp0_addr, port_csp0_shadow, 8, 1);
#endif
#ifdef CONFIG_ETRAX_IDE_G27_RESET
	*R_PORT_G_DATA = 0; /* de-assert bus-reset */
#endif 

	/* make a dummy read to set the ata controller in a proper state */
	dummy = *R_ATA_STATUS_DATA;
  
	*R_ATA_CONFIG = ( IO_FIELD( R_ATA_CONFIG, enable,     1 ) |
			  IO_FIELD( R_ATA_CONFIG, dma_strobe, ATA_DMA2_STROBE ) |
			  IO_FIELD( R_ATA_CONFIG, dma_hold,   ATA_DMA2_HOLD ) |
			  IO_FIELD( R_ATA_CONFIG, pio_setup,  ATA_PIO4_SETUP ) |
			  IO_FIELD( R_ATA_CONFIG, pio_strobe, ATA_PIO4_STROBE ) |
			  IO_FIELD( R_ATA_CONFIG, pio_hold,   ATA_PIO4_HOLD ) );

	*R_ATA_CTRL_DATA = ( IO_STATE( R_ATA_CTRL_DATA, rw,   read) |
			     IO_FIELD( R_ATA_CTRL_DATA, addr, 1   ) );

	while(*R_ATA_STATUS_DATA & IO_MASK(R_ATA_STATUS_DATA, busy)); /* wait for busy flag*/

	*R_IRQ_MASK0_SET = ( IO_STATE( R_IRQ_MASK0_SET, ata_irq0, set ) |
			     IO_STATE( R_IRQ_MASK0_SET, ata_irq1, set ) |
			     IO_STATE( R_IRQ_MASK0_SET, ata_irq2, set ) |
			     IO_STATE( R_IRQ_MASK0_SET, ata_irq3, set ) );

	printk("ide: waiting %d seconds for drives to regain consciousness\n", CONFIG_ETRAX_IDE_DELAY);

	h = jiffies + (CONFIG_ETRAX_IDE_DELAY * HZ);
	while(jiffies < h) ;

  /* reset the dma channels we will use */

	RESET_DMA(ATA_TX_DMA_NBR);
	RESET_DMA(ATA_RX_DMA_NBR);
	WAIT_DMA(ATA_TX_DMA_NBR);
	WAIT_DMA(ATA_RX_DMA_NBR);

}

static etrax_dma_descr mydescr;

/*
 * The following routines are mainly used by the ATAPI drivers.
 *
 * These routines will round up any request for an odd number of bytes,
 * so if an odd bytecount is specified, be sure that there's at least one
 * extra byte allocated for the buffer.
 */
static void 
e100_atapi_input_bytes (ide_drive_t *drive, void *buffer, unsigned int bytecount)
{
	ide_ioreg_t data_reg = IDE_DATA_REG;

	D(printk("atapi_input_bytes, dreg 0x%x, buffer 0x%x, count %d\n",
		 data_reg, buffer, bytecount));
	
	if(bytecount & 1) {
		printk("warning, odd bytecount in cdrom_in_bytes = %d.\n", bytecount);
		bytecount++; /* to round off */
	}
	
	/* make sure the DMA channel is available */
	RESET_DMA(ATA_RX_DMA_NBR);
	WAIT_DMA(ATA_RX_DMA_NBR); 
	
	/* setup DMA descriptor */
	
	mydescr.sw_len = bytecount;
	mydescr.ctrl   = d_eol;
	mydescr.buf    = virt_to_phys(buffer);
	
	/* start the dma channel */
	
	*R_DMA_CH3_FIRST = virt_to_phys(&mydescr);
	*R_DMA_CH3_CMD   = IO_STATE(R_DMA_CH3_CMD, cmd, start);
	
	/* initiate a multi word dma read using PIO handshaking */
	
	*R_ATA_TRANSFER_CNT = IO_FIELD(R_ATA_TRANSFER_CNT, count, bytecount >> 1);
	
	*R_ATA_CTRL_DATA = data_reg |
		IO_STATE(R_ATA_CTRL_DATA, rw,       read) |
		IO_STATE(R_ATA_CTRL_DATA, src_dst,  dma) |
		IO_STATE(R_ATA_CTRL_DATA, handsh,   pio) |
		IO_STATE(R_ATA_CTRL_DATA, multi,    on) |
		IO_STATE(R_ATA_CTRL_DATA, dma_size, word);
	
	/* wait for completion */
	
	LED_DISK_READ(1);
	WAIT_DMA(ATA_RX_DMA_NBR);
	LED_DISK_READ(0);

#if 0
        /* old polled transfer code
	 * this should be moved into a new function that can do polled
	 * transfers if DMA is not available
	 */
        
        /* initiate a multi word read */
        
        *R_ATA_TRANSFER_CNT = wcount << 1;
        
        *R_ATA_CTRL_DATA = data_reg |
                IO_STATE(R_ATA_CTRL_DATA, rw,       read) |
                IO_STATE(R_ATA_CTRL_DATA, src_dst,  register) |
                IO_STATE(R_ATA_CTRL_DATA, handsh,   pio) |
                IO_STATE(R_ATA_CTRL_DATA, multi,    on) |
                IO_STATE(R_ATA_CTRL_DATA, dma_size, word);
        
        /* svinto has a latency until the busy bit actually is set */
        
        nop(); nop();
        nop(); nop();
        nop(); nop();
        nop(); nop();
        nop(); nop();
        
        /* unit should be busy during multi transfer */
        while((status = *R_ATA_STATUS_DATA) & IO_MASK(R_ATA_STATUS_DATA, busy)) {
                while(!(status & IO_MASK(R_ATA_STATUS_DATA, dav)))
                        status = *R_ATA_STATUS_DATA;
                *ptr++ = (unsigned short)(status & 0xffff);