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ARM 嵌入式 系统 设计与实例开发 实验教材 二源码

		lda	[%g1] ASI_M_BYPASS, %g1		! ptr to level 1 pg_table
		srl	%g1, 0x4, %g1
		sll	%g1, 0x8, %g1			! make phys addr for l1 tbl

		lda	[%g1] ASI_M_BYPASS, %g2		! get level1 entry for 0x0
		add	%g1, 0x3c0, %g3			! XXX AWAY WITH EMPIRICALS
		sta	%g2, [%g3] ASI_M_BYPASS		! place at KERNBASE entry
		b	go_to_highmem
		 nop					! wheee....

		/* This remaps the kernel on Sun4/4xx machines
		 * that have the Sun Mutant Three Level MMU.
		 * It's like a platypus, Sun didn't have the
		 * SRMMU in conception so they kludged the three
		 * level logic in the regular Sun4 MMU probably.
		 *
		 * Basically, you take each entry in the top level
		 * directory that maps the low 3MB starting at
		 * address zero and put the mapping in the KERNBASE
		 * slots.  These top level pgd's are called regmaps.
		 */
sun4_mutant_remap:
		or	%g0, %g0, %g3		! source base
		sethi	%hi(KERNBASE), %g4	! destination base
		or	%g4, %lo(KERNBASE), %g4
		sethi	%hi(0x300000), %g5
		or	%g5, %lo(0x300000), %g5	! upper bound 3MB
		or	%g0, 0x1, %l6
		sll	%l6, 24, %l6		! Regmap mapping size
		add	%g3, 0x2, %g3		! Base magic
		add	%g4, 0x2, %g4		! Base magic

		/* Main remapping loop on Sun4-Mutant-MMU.
		 * "I am not an animal..." -Famous Mutant Person
		 */
sun4_mutant_loop:
		lduha	[%g3] ASI_REGMAP, %g2	! Get lower entry
		stha	%g2, [%g4] ASI_REGMAP	! Store in high entry
		add	%g4, %l6, %g4		! Move up high memory ptr
		subcc	%g3, %g5, %g0		! Reached our limit?
		blu	sun4_mutant_loop	! Nope, loop again
		 add	%g3, %l6, %g3		! delay, Move up low ptr
		b	go_to_highmem		! Jump to high memory.
		 nop

		/* The following is for non-4/4xx sun4 MMU's. */
sun4_normal_remap:
		mov	0, %g3			! source base
		set	KERNBASE, %g4		! destination base
		set	0x300000, %g5		! upper bound 3MB
		mov	1, %l6
		sll	%l6, 18, %l6		! sun4 mmu segmap size
sun4_normal_loop:
		lduha	[%g3] ASI_SEGMAP, %g6	! load phys_seg
		stha	%g6, [%g4] ASI_SEGMAP	! stort new virt mapping
		add	%g3, %l6, %g3		! increment source pointer
		subcc	%g3, %g5, %g0		! reached limit?
		blu	sun4_normal_loop	! nope, loop again
		 add	%g4, %l6, %g4		! delay, increment dest ptr
		b	go_to_highmem
		 nop

		/* The following works for Sun4c MMU's */
sun4c_remap:
		mov	0, %g3			! source base
		set	KERNBASE, %g4		! destination base
		set	0x300000, %g5		! upper bound 3MB
		mov	1, %l6
		sll	%l6, 18, %l6		! sun4c mmu segmap size
sun4c_remap_loop:
		lda	[%g3] ASI_SEGMAP, %g6	! load phys_seg
		sta	%g6, [%g4] ASI_SEGMAP   ! store new virt mapping
		add	%g3, %l6, %g3		! Increment source ptr
		subcc	%g3, %g5, %g0		! Reached limit?
		bl	sun4c_remap_loop	! Nope, loop again
		 add	%g4, %l6, %g4		! delay, Increment dest ptr

/* Now do a non-relative jump so that PC is in high-memory */
go_to_highmem:
		set	execute_in_high_mem, %g1
		jmpl	%g1, %g0
		 nop

	/* This is to align init_task_union properly, be careful. -DaveM */
	.align	8192

/* The code above should be at beginning and we have to take care about
 * short jumps, as branching to .text.init section from .text is usually
 * impossible */
		__INIT
/* Acquire boot time privileged register values, this will help debugging.
 * I figure out and store nwindows and nwindowsm1 later on.
 */
execute_in_high_mem:
		mov	%l0, %o0		! put back romvec
		mov	%l1, %o1		! and debug_vec

		sethi	%hi( C_LABEL(prom_vector_p) ), %g1
		st	%o0, [%g1 + %lo( C_LABEL(prom_vector_p) )]

		sethi	%hi( C_LABEL(linux_dbvec) ), %g1
		st	%o1, [%g1 + %lo( C_LABEL(linux_dbvec) )]

		ld	[%o0 + 0x4], %o3
		and	%o3, 0x3, %o5			! get the version

		cmp	%o3, 0x2			! a v2 prom?
		be	found_version
		 nop

		/* [e-mail] */
		cmp	%o3, 0x3			! a v3 prom?
		be	found_version
		 nop

/* Old sun4's pass our load address into %o0 instead of the prom
 * pointer. On sun4's you have to hard code the romvec pointer into
 * your code. Sun probably still does that because they don't even
 * trust their own "OpenBoot" specifications.
 */
		set	LOAD_ADDR, %g6
		cmp	%o0, %g6		! an old sun4?
		be	sun4_init
		 nop

found_version:
#ifdef CONFIG_SUN4
/* For people who try sun4 kernels, even if Configure.help advises them. */
		ld	[%g7 + 0x68], %o1
		set	sun4cdm_notsup, %o0
		call	%o1
		 nop
		b	halt_me
		 nop
#endif
/* Get the machine type via the mysterious romvec node operations. */

		add	%g7, 0x1c, %l1		
		ld	[%l1], %l0
		ld	[%l0], %l0
		call 	%l0
		 or	%g0, %g0, %o0		! next_node(0) = first_node
		or	%o0, %g0, %g6

		sethi	%hi( C_LABEL(cputypvar) ), %o1	! First node has cpu-arch
		or	%o1, %lo( C_LABEL(cputypvar) ), %o1
		sethi	%hi( C_LABEL(cputypval) ), %o2	! information, the string
		or	%o2, %lo( C_LABEL(cputypval) ), %o2
		ld	[%l1], %l0		! 'compatibility' tells
		ld	[%l0 + 0xc], %l0	! that we want 'sun4x' where
		call	%l0			! x is one of '', 'c', 'm',
		 nop				! 'd' or 'e'. %o2 holds pointer
						! to a buf where above string
						! will get stored by the prom.

		subcc	%o0, %g0, %g0
		bpos	got_prop		! Got the property
		 nop

		or	%g6, %g0, %o0
		sethi	%hi( C_LABEL(cputypvar_sun4m) ), %o1
		or	%o1, %lo( C_LABEL(cputypvar_sun4m) ), %o1
		sethi	%hi( C_LABEL(cputypval) ), %o2
		or	%o2, %lo( C_LABEL(cputypval) ), %o2
		ld	[%l1], %l0
		ld	[%l0 + 0xc], %l0
		call	%l0
		 nop

got_prop:
		set	C_LABEL(cputypval), %o2
		ldub	[%o2 + 0x4], %l1

		cmp	%l1, ' '
		be	1f
		 cmp	%l1, 'c'
		be	1f
		 cmp	%l1, 'm'
		be	1f
		 cmp	%l1, 's'
		be	1f
		 cmp	%l1, 'd'
		be	1f
		 cmp	%l1, 'e'
		be	no_sun4e_here		! Could be a sun4e.
		 nop
		b	no_sun4u_here		! AIEEE, a V9 sun4u... Get our BIG BROTHER kernel :))
		 nop

1:		set	C_LABEL(cputypval), %l1
		ldub	[%l1 + 0x4], %l1
		cmp	%l1, 'm'		! Test for sun4d, sun4e ?
		be	sun4m_init
		 cmp	%l1, 's'		! Treat sun4s as sun4m
		be	sun4m_init
		 cmp	%l1, 'd'		! Let us see how the beast will die
		be	sun4d_init
		 nop

		/* Jump into mmu context zero. */
		set	AC_CONTEXT, %g1
		stba	%g0, [%g1] ASI_CONTROL

		b	sun4c_continue_boot
		 nop

/* CPUID in bootbus can be found at PA 0xff0140000 */
#define SUN4D_BOOTBUS_CPUID     0xf0140000

sun4d_init:
	/* Need to patch call to handler_irq */
	set	C_LABEL(patch_handler_irq), %g4
	set	C_LABEL(sun4d_handler_irq), %g5
	sethi	%hi(0x40000000), %g3		! call
	sub	%g5, %g4, %g5
	srl	%g5, 2, %g5
	or	%g5, %g3, %g5
	st	%g5, [%g4]

#ifdef CONFIG_SMP
	/* Get our CPU id out of bootbus */
	set     SUN4D_BOOTBUS_CPUID, %g3
	lduba   [%g3] ASI_M_CTL, %g3
	and     %g3, 0xf8, %g3
	srl     %g3, 3, %g4
	sta     %g4, [%g0] ASI_M_VIKING_TMP1
	sethi	%hi(boot_cpu_id), %g5
	stb	%g4, [%g5 + %lo(boot_cpu_id)]
	sll	%g4, 2, %g4
	sethi	%hi(boot_cpu_id4), %g5
	stb	%g4, [%g5 + %lo(boot_cpu_id4)]
#endif

	/* Fall through to sun4m_init */

sun4m_init:
	/* XXX Fucking Cypress... */
	lda	[%g0] ASI_M_MMUREGS, %g5
	srl	%g5, 28, %g4

	cmp	%g4, 1
	bne	1f
	 srl	%g5, 24, %g4

	and	%g4, 0xf, %g4
	cmp	%g4, 7		/* This would be a HyperSparc. */

	bne	2f
	 nop

1:

#define PATCH_IT(dst, src)	\
	set	(dst), %g5;	\
	set	(src), %g4;	\
	ld	[%g4], %g3;	\
	st	%g3, [%g5];	\
	ld	[%g4+0x4], %g3;	\
	st	%g3, [%g5+0x4];

	/* Signed multiply. */
	PATCH_IT(.mul, .mul_patch)
	PATCH_IT(.mul+0x08, .mul_patch+0x08)

	/* Signed remainder. */
	PATCH_IT(.rem, .rem_patch)
	PATCH_IT(.rem+0x08, .rem_patch+0x08)
	PATCH_IT(.rem+0x10, .rem_patch+0x10)
	PATCH_IT(.rem+0x18, .rem_patch+0x18)
	PATCH_IT(.rem+0x20, .rem_patch+0x20)
	PATCH_IT(.rem+0x28, .rem_patch+0x28)

	/* Signed division. */
	PATCH_IT(.div, .div_patch)
	PATCH_IT(.div+0x08, .div_patch+0x08)
	PATCH_IT(.div+0x10, .div_patch+0x10)
	PATCH_IT(.div+0x18, .div_patch+0x18)
	PATCH_IT(.div+0x20, .div_patch+0x20)

	/* Unsigned multiply. */
	PATCH_IT(.umul, .umul_patch)
	PATCH_IT(.umul+0x08, .umul_patch+0x08)

	/* Unsigned remainder. */
	PATCH_IT(.urem, .urem_patch)
	PATCH_IT(.urem+0x08, .urem_patch+0x08)
	PATCH_IT(.urem+0x10, .urem_patch+0x10)
	PATCH_IT(.urem+0x18, .urem_patch+0x18)

	/* Unsigned division. */
	PATCH_IT(.udiv, .udiv_patch)
	PATCH_IT(.udiv+0x08, .udiv_patch+0x08)
	PATCH_IT(.udiv+0x10, .udiv_patch+0x10)

#undef PATCH_IT

/* Ok, the PROM could have done funny things and apple cider could still
 * be sitting in the fault status/address registers.  Read them all to
 * clear them so we don't get magic faults later on.
 */
/* This sucks, apparently this makes Vikings call prom panic, will fix later */
2:
		rd	%psr, %o1
		srl	%o1, 28, %o1		! Get a type of the CPU

		subcc	%o1, 4, %g0		! TI: Viking or MicroSPARC
		be	sun4c_continue_boot
		 nop

		set	AC_M_SFSR, %o0
		lda	[%o0] ASI_M_MMUREGS, %g0
		set	AC_M_SFAR, %o0
		lda	[%o0] ASI_M_MMUREGS, %g0

		/* Fujitsu MicroSPARC-II has no asynchronous flavors of FARs */
		subcc	%o1, 0, %g0
		be	sun4c_continue_boot
		 nop

		set	AC_M_AFSR, %o0
		lda	[%o0] ASI_M_MMUREGS, %g0
		set	AC_M_AFAR, %o0
		lda	[%o0] ASI_M_MMUREGS, %g0
		 nop


sun4c_continue_boot:


/* Aieee, now set PC and nPC, enable traps, give ourselves a stack and it's
 * show-time!
 */

		sethi	%hi( C_LABEL(cputyp) ), %o0