📄 danxiangquanqiao_z.mdl
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PortDimensions "-1"
SampleTime "-1"
DataType "auto"
OutDataType "sfix(16)"
OutScaling "2^0"
SignalType "auto"
SamplingMode "auto"
LatchByDelayingOutsideSignal off
LatchByCopyingInsideSignal off
Interpolate on
}
Block {
BlockType Logic
Operator "AND"
Inputs "2"
AllPortsSameDT on
OutDataTypeMode "Logical (see Configuration Parameters: Optimiza"
"tion)"
LogicDataType "uint(8)"
SampleTime "-1"
}
Block {
BlockType Mux
Inputs "4"
DisplayOption "none"
UseBusObject off
BusObject "BusObject"
NonVirtualBus off
}
Block {
BlockType Outport
Port "1"
UseBusObject off
BusObject "BusObject"
BusOutputAsStruct off
PortDimensions "-1"
SampleTime "-1"
DataType "auto"
OutDataType "sfix(16)"
OutScaling "2^0"
SignalType "auto"
SamplingMode "auto"
OutputWhenDisabled "held"
InitialOutput "[]"
}
Block {
BlockType PMComponent
SubClassName "unknown"
}
Block {
BlockType PMIOPort
}
Block {
BlockType Saturate
UpperLimit "0.5"
LowerLimit "-0.5"
LinearizeAsGain on
ZeroCross on
SampleTime "-1"
}
Block {
BlockType Scope
ModelBased off
TickLabels "OneTimeTick"
ZoomMode "on"
Grid "on"
TimeRange "auto"
YMin "-5"
YMax "5"
SaveToWorkspace off
SaveName "ScopeData"
LimitDataPoints on
MaxDataPoints "5000"
Decimation "1"
SampleInput off
SampleTime "-1"
}
Block {
BlockType "S-Function"
FunctionName "system"
SFunctionModules "''"
PortCounts "[]"
}
Block {
BlockType SubSystem
ShowPortLabels on
Permissions "ReadWrite"
PermitHierarchicalResolution "All"
SystemSampleTime "-1"
RTWFcnNameOpts "Auto"
RTWFileNameOpts "Auto"
SimViewingDevice off
DataTypeOverride "UseLocalSettings"
MinMaxOverflowLogging "UseLocalSettings"
}
Block {
BlockType Sum
IconShape "rectangular"
Inputs "++"
InputSameDT on
OutDataTypeMode "Same as first input"
OutDataType "sfix(16)"
OutScaling "2^0"
LockScale off
RndMeth "Floor"
SaturateOnIntegerOverflow on
SampleTime "-1"
}
Block {
BlockType Switch
Criteria "u2 >= Threshold"
Threshold "0"
InputSameDT on
OutDataTypeMode "Inherit via internal rule"
RndMeth "Floor"
SaturateOnIntegerOverflow on
ZeroCross on
SampleTime "-1"
}
Block {
BlockType Terminator
}
}
AnnotationDefaults {
HorizontalAlignment "center"
VerticalAlignment "middle"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
FontName "arial"
FontSize 10
FontWeight "normal"
FontAngle "normal"
}
LineDefaults {
FontName "arial"
FontSize 9
FontWeight "normal"
FontAngle "normal"
}
System {
Name "danxiangquanqiao_Z"
Location [2, 74, 1014, 722]
Open on
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
ZoomFactor "80"
ReportName "simulink-default.rpt"
Block {
BlockType Reference
Name "Current Measurement"
Ports [0, 1, 0, 0, 0, 1, 1]
Position [255, 33, 280, 57]
SourceBlock "powerlib/Measurements/Current Measurement"
SourceType "Current Measurement"
ShowPortLabels on
PhasorSimulation off
OutputType "Complex"
PSBequivalent "0"
}
Block {
BlockType Reference
Name "DC Voltage Source"
Ports [0, 0, 0, 0, 0, 1, 1]
Position [105, 175, 125, 210]
Orientation "up"
SourceBlock "powerlib/Electrical\nSources/DC Voltage Source"
SourceType "DC Voltage Source"
ShowPortLabels on
Amplitude "20"
Measurements "Voltage"
}
Block {
BlockType Reference
Name "Diode"
Ports [0, 0, 0, 0, 0, 1, 1]
Position [140, 25, 195, 65]
FontSize 10
SourceBlock "powerlib/Power\nElectronics/Diode"
SourceType "Diode"
ShowPortLabels on
Ron "0.001"
Lon "0"
Vf "0.8"
IC "0"
Rs "500"
Cs "250e-9"
Measurements off
}
Block {
BlockType Reference
Name "IGBT/Diode"
Ports [1, 1, 0, 0, 0, 1, 1]
Position [910, 13, 970, 57]
SourceBlock "powerlib/Power\nElectronics/IGBT//Diode"
SourceType "IGBT/Diode"
ShowPortLabels on
Ron "1e-3"
Rs "1e5"
Cs "inf"
Measurements on
}
Block {
BlockType Reference
Name "IGBT/Diode1"
Ports [1, 1, 0, 0, 0, 1, 1]
Position [680, 273, 740, 317]
SourceBlock "powerlib/Power\nElectronics/IGBT//Diode"
SourceType "IGBT/Diode"
ShowPortLabels on
Ron "1e-3"
Rs "1e5"
Cs "inf"
Measurements on
}
Block {
BlockType Reference
Name "IGBT/Diode2"
Ports [1, 1, 0, 0, 0, 1, 1]
Position [925, 283, 985, 327]
SourceBlock "powerlib/Power\nElectronics/IGBT//Diode"
SourceType "IGBT/Diode"
ShowPortLabels on
Ron "1e-3"
Rs "1e5"
Cs "inf"
Measurements on
}
Block {
BlockType Reference
Name "IGBT/Diode3"
Ports [1, 1, 0, 0, 0, 1, 1]
Position [685, 98, 745, 142]
SourceBlock "powerlib/Power\nElectronics/IGBT//Diode"
SourceType "IGBT/Diode"
ShowPortLabels on
Ron "1e-3"
Rs "1e5"
Cs "inf"
Measurements on
}
Block {
BlockType Logic
Name "Logical\nOperator"
Ports [2, 1]
Position [385, 477, 415, 508]
Operator "OR"
AllPortsSameDT off
OutDataTypeMode "Boolean"
}
Block {
BlockType Logic
Name "Logical\nOperator1"
Ports [2, 1]
Position [380, 662, 410, 693]
Operator "OR"
AllPortsSameDT off
OutDataTypeMode "Boolean"
}
Block {
BlockType Logic
Name "Logical\nOperator2"
Ports [2, 1]
Position [905, 507, 935, 538]
Operator "OR"
AllPortsSameDT off
OutDataTypeMode "Boolean"
}
Block {
BlockType Logic
Name "Logical\nOperator3"
Ports [2, 1]
Position [885, 727, 915, 758]
Operator "OR"
AllPortsSameDT off
OutDataTypeMode "Boolean"
}
Block {
BlockType DiscretePulseGenerator
Name "Pulse\nGenerator"
Ports [0, 1]
Position [785, 458, 830, 492]
PulseType "Time based"
Period "0.0001"
PulseWidth "50"
}
Block {
BlockType DiscretePulseGenerator
Name "Pulse\nGenerator1"
Ports [0, 1]
Position [220, 503, 265, 537]
PulseType "Time based"
Period "0.0001"
PulseWidth "20"
PhaseDelay "0.00008"
}
Block {
BlockType DiscretePulseGenerator
Name "Pulse\nGenerator2"
Ports [0, 1]
Position [220, 693, 265, 727]
PulseType "Time based"
Period "0.0001"
PulseWidth "20"
PhaseDelay "0.00008"
}
Block {
BlockType DiscretePulseGenerator
Name "Pulse\nGenerator3"
Ports [0, 1]
Position [740, 518, 785, 552]
PulseType "Time based"
Period "0.0001"
PulseWidth "20"
PhaseDelay "0.00008"
}
Block {
BlockType DiscretePulseGenerator
Name "Pulse\nGenerator4"
Ports [0, 1]
Position [710, 743, 755, 777]
PulseType "Time based"
Period "0.0001"
PulseWidth "20"
PhaseDelay "0.00008"
}
Block {
BlockType DiscretePulseGenerator
Name "Pulse\nGenerator5"
Ports [0, 1]
Position [755, 673, 800, 707]
PulseType "Time based"
Period "0.0001"
PulseWidth "50"
PhaseDelay "0.00005"
}
Block {
BlockType DiscretePulseGenerator
Name "Pulse\nGenerator6"
Ports [0, 1]
Position [245, 438, 290, 472]
PulseType "Time based"
Period "0.0001"
PulseWidth "20"
}
Block {
BlockType DiscretePulseGenerator
Name "Pulse\nGenerator7"
Ports [0, 1]
Position [260, 618, 305, 652]
PulseType "Time based"
Period "0.0001"
PulseWidth "80"
PhaseDelay "-0.00008"
}
Block {
BlockType DiscretePulseGenerator
Name "Pulse\nGenerator8"
Ports [0, 1]
Position [40, 493, 85, 527]
PulseType "Time based"
Period "0.0001"
PulseWidth "80"
}
Block {
BlockType Scope
Name "Scope"
Ports [3]
Position [1060, 329, 1210, 581]
Floating off
Location [5, 45, 1021, 729]
Open off
NumInputPorts "3"
ZoomMode "xonly"
List {
ListType AxesTitles
axes1 "%<SignalLabel>"
axes2 "%<SignalLabel>"
axes3 "%<SignalLabel>"
}
YMin "-5~-5~-5"
YMax "5~5~5"
DataFormat "StructureWithTime"
SampleTime "0"
}
Block {
BlockType Scope
Name "Scope1"
Ports [2]
Position [130, 568, 200, 757]
Floating off
Location [5, 45, 1021, 729]
Open off
NumInputPorts "2"
ZoomMode "xonly"
List {
ListType AxesTitles
axes1 "%<SignalLabel>"
axes2 "%<SignalLabel>"
}
YMin "-5~-5"
YMax "5~5"
SaveName "ScopeData1"
DataFormat "StructureWithTime"
SampleTime "0"
}
Block {
BlockType Reference
Name "Series RLC Branch"
Ports [0, 0, 0, 0, 0, 1, 1]
Position [875, 181, 945, 209]
SourceBlock "powerlib/Elements/Series RLC Branch"
SourceType "Series RLC Branch"
PhysicalDomain "powersysdomain"
SubClassName "unknown"
LeftPortType "p1"
RightPortType "p1"
LConnTagsString "__new0"
RConnTagsString "__new0"
BranchType "RL"
Resistance "10"
Inductance "0"
SetiL0 off
InitialCurrent "0"
Capacitance "1e-6"
Setx0 off
InitialVoltage "0"
Measurements "Branch voltage and current"
}
Block {
BlockType Reference
Name "Series RLC Branch1"
Ports [0, 0, 0, 0, 0, 1, 1]
Position [420, 38, 460, 52]
SourceBlock "powerlib/Elements/Series RLC Branch"
SourceType "Series RLC Branch"
PhysicalDomain "powersysdomain"
SubClassName "unknown"
LeftPortType "p1"
RightPortType "p1"
LConnTagsString "__new0"
RConnTagsString "__new0"
BranchType "L"
Resistance "10"
Inductance "160e-3"
SetiL0 off
InitialCurrent "0"
Capacitance "1e-6"
Setx0 off
InitialVoltage "0"
Measurements "Branch voltage and current"
}
Block {
BlockType Reference
Name "Series RLC Branch2"
Ports [0, 0, 0, 0, 0, 1, 1]
Position [420, 338, 460, 352]
SourceBlock "powerlib/Elements/Series RLC Branch"
SourceType "Series RLC Branch"
PhysicalDomain "powersysdomain"
SubClassName "unknown"
LeftPortType "p1"
RightPortType "p1"
LConnTagsString "__new0"
RConnTagsString "__new0"
BranchType "L"
Resistance "10"
Inductance "160e-3"
SetiL0 off
InitialCurrent "0"
Capacitance "1e-6"
Setx0 off
InitialVoltage "0"
Measurements "Branch voltage and current"
}
Block {
BlockType Reference
Name "Series RLC Branch3"
Ports [0, 0, 0, 0, 0, 1, 1]
Position [333, 165, 347, 205]
Orientation "down"
NamePlacement "alternate"
SourceBlock "powerlib/Elements/Series RLC Branch"
SourceType "Series RLC Branch"
PhysicalDomain "powersysdomain"
SubClassName "unknown"
LeftPortType "p1"
RightPortType "p1"
LConnTagsString "__new0"
RConnTagsString "__new0"
BranchType "C"
Resistance "10"
Inductance "0.003"
SetiL0 off
InitialCurrent "0"
Capacitance "330e-6"
Setx0 on
InitialVoltage "0"
Measurements "Branch voltage and current"
}
Block {
BlockType Reference
Name "Series RLC Branch4"
Ports [0, 0, 0, 0, 0, 1, 1]
Position [548, 160, 562, 200]
Orientation "down"
NamePlacement "alternate"
SourceBlock "powerlib/Elements/Series RLC Branch"
SourceType "Series RLC Branch"
PhysicalDomain "powersysdomain"
SubClassName "unknown"
LeftPortType "p1"
RightPortType "p1"
LConnTagsString "__new0"
RConnTagsString "__new0"
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