dds.hif

FPGA实现DDS

# macro_sequence

# end
# entity
LPM_SHIFTREG
# storage
db|dds.(8).cnf
db|dds.(8).cnf
# case_insensitive
# source_file
c:|altera|80|quartus|libraries|megafunctions|LPM_SHIFTREG.tdf
73c9c8ade8e954637797bb4bfbede563
6
# user_parameter {
LPM_WIDTH
111
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
SHIFTOUT
-1
3
SHIFTIN
-1
3
Q99
-1
3
Q98
-1
3
Q97
-1
3
Q96
-1
3
Q95
-1
3
Q94
-1
3
Q93
-1
3
Q92
-1
3
Q91
-1
3
Q90
-1
3
Q9
-1
3
Q89
-1
3
Q88
-1
3
Q87
-1
3
Q86
-1
3
Q85
-1
3
Q84
-1
3
Q83
-1
3
Q82
-1
3
Q81
-1
3
Q80
-1
3
Q8
-1
3
Q79
-1
3
Q78
-1
3
Q77
-1
3
Q76
-1
3
Q75
-1
3
Q74
-1
3
Q73
-1
3
Q72
-1
3
Q71
-1
3
Q70
-1
3
Q7
-1
3
Q69
-1
3
Q68
-1
3
Q67
-1
3
Q66
-1
3
Q65
-1
3
Q64
-1
3
Q63
-1
3
Q62
-1
3
Q61
-1
3
Q60
-1
3
Q6
-1
3
Q59
-1
3
Q58
-1
3
Q57
-1
3
Q56
-1
3
Q55
-1
3
Q54
-1
3
Q53
-1
3
Q52
-1
3
Q51
-1
3
Q50
-1
3
Q5
-1
3
Q49
-1
3
Q48
-1
3
Q47
-1
3
Q46
-1
3
Q45
-1
3
Q44
-1
3
Q43
-1
3
Q42
-1
3
Q41
-1
3
Q40
-1
3
Q4
-1
3
Q39
-1
3
Q38
-1
3
Q37
-1
3
Q36
-1
3
Q35
-1
3
Q34
-1
3
Q33
-1
3
Q32
-1
3
Q31
-1
3
Q30
-1
3
Q3
-1
3
Q29
-1
3
Q28
-1
3
Q27
-1
3
Q26
-1
3
Q25
-1
3
Q24
-1
3
Q23
-1
3
Q22
-1
3
Q21
-1
3
Q20
-1
3
Q2
-1
3
Q19
-1
3
Q18
-1
3
Q17
-1
3
Q16
-1
3
Q15
-1
3
Q14
-1
3
Q13
-1
3
Q12
-1
3
Q110
-1
3
Q11
-1
3
Q109
-1
3
Q108
-1
3
Q107
-1
3
Q106
-1
3
Q105
-1
3
Q104
-1
3
Q103
-1
3
Q102
-1
3
Q101
-1
3
Q100
-1
3
Q10
-1
3
Q1
-1
3
Q0
-1
3
ENABLE
-1
3
CLOCK
-1
3
ACLR
-1
3
}
# include_file {
c:|altera|80|quartus|libraries|megafunctions|dffeea.inc
55d29d20f7e852c37746bec4e2495ec
c:|altera|80|quartus|libraries|megafunctions|aglobal80.inc
9274497d636e3ed37111b8c54bf938
c:|altera|80|quartus|libraries|megafunctions|lpm_constant.inc
dcde44eee59335c1e2fe75d574f9646
}
# macro_sequence

# end
# entity
sld_mbpmg
# storage
db|dds.(9).cnf
db|dds.(9).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|80|quartus|libraries|megafunctions|sld_mbpmg.vhd
d179503157e1445256da6d0c6d19987
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
data_bits
37
PARAMETER_SIGNED_DEC
USR
pattern_bits
3
PARAMETER_SIGNED_DEC
USR
async_enabled
0
PARAMETER_SIGNED_DEC
USR
sync_enabled
1
PARAMETER_SIGNED_DEC
USR
pipeline
1
PARAMETER_SIGNED_DEC
USR
 constraint(data_in)
36 downto 0
PARAMETER_STRING
USR
 constraint(pattern_in)
110 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|80|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
sld_sbpmg
# storage
db|dds.(10).cnf
db|dds.(10).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|80|quartus|libraries|megafunctions|sld_mbpmg.vhd
d179503157e1445256da6d0c6d19987
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
async_enabled
0
PARAMETER_SIGNED_DEC
USR
pipeline
1
PARAMETER_SIGNED_DEC
USR
}
# lmf
c:|altera|80|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
sld_ela_trigger_flow_mgr
# storage
db|dds.(11).cnf
db|dds.(11).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|80|quartus|libraries|megafunctions|sld_ela_trigger_flow_mgr.vhd
54b4e96651b97ec28a57c8b6d87fce
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
trigger_level
1
PARAMETER_SIGNED_DEC
USR
segment_size_bits
8
PARAMETER_SIGNED_DEC
USR
state_bits
11
PARAMETER_SIGNED_DEC
USR
power_up_trigger
0
PARAMETER_SIGNED_DEC
USR
inversion_mask_length
1
PARAMETER_SIGNED_DEC
USR
inversion_mask
0
PARAMETER_UNSIGNED_BIN
USR
 constraint(inversion_mask)
0 downto 0
PARAMETER_STRING
USR
 constraint(condition_met)
0 downto 0
PARAMETER_STRING
USR
 constraint(post_fill_count)
7 downto 0
PARAMETER_STRING
USR
 constraint(current_state)
10 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|80|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
LPM_SHIFTREG
# storage
db|dds.(12).cnf
db|dds.(12).cnf
# case_insensitive
# source_file
c:|altera|80|quartus|libraries|megafunctions|LPM_SHIFTREG.tdf
73c9c8ade8e954637797bb4bfbede563
6
# user_parameter {
LPM_WIDTH
10
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
SHIFTOUT
-1
3
SHIFTIN
-1
3
Q0
-1
3
ENABLE
-1
3
CLOCK
-1
3
ACLR
-1
3
}
# include_file {
c:|altera|80|quartus|libraries|megafunctions|dffeea.inc
55d29d20f7e852c37746bec4e2495ec
c:|altera|80|quartus|libraries|megafunctions|aglobal80.inc
9274497d636e3ed37111b8c54bf938
c:|altera|80|quartus|libraries|megafunctions|lpm_constant.inc
dcde44eee59335c1e2fe75d574f9646
}
# macro_sequence

# end
# entity
sld_buffer_manager
# storage
db|dds.(13).cnf
db|dds.(13).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
c:|altera|80|quartus|libraries|megafunctions|sld_buffer_manager.vhd
4c63f6d27d9a67852bb11a567329bfe3
4
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
ip_major_version
6
PARAMETER_SIGNED_DEC
USR
ip_minor_version
0
PARAMETER_SIGNED_DEC
USR
common_ip_version
0
PARAMETER_SIGNED_DEC
USR
address_bits
8
PARAMETER_SIGNED_DEC
USR
segment_size_bits
8
PARAMETER_SIGNED_DEC
USR
num_segments_bits
1
PARAMETER_SIGNED_DEC
USR
 constraint(address)
7 downto 0
PARAMETER_STRING
USR
 constraint(post_count)
7 downto 0
PARAMETER_STRING
USR
 constraint(current_segment)
0 downto 0
PARAMETER_STRING
USR
 constraint(current_offset)
7 downto 0
PARAMETER_STRING
USR
 constraint(last_trigger_address)
7 downto 0
PARAMETER_STRING
USR
 constraint(last_buffer_write_address)
7 downto 0
PARAMETER_STRING
USR
 constraint(trigger_write_address)
7 downto 0
PARAMETER_STRING
USR
}
# lmf
c:|altera|80|quartus|lmf|maxplus2.lmf
9a59d39b0706640b4b2718e8a1ff1f
# macro_sequence

# end
# entity
LPM_SHIFTREG
# storage
db|dds.(14).cnf
db|dds.(14).cnf
# case_insensitive
# source_file
c:|altera|80|quartus|libraries|megafunctions|LPM_SHIFTREG.tdf
73c9c8ade8e954637797bb4bfbede563
6
# user_parameter {
LPM_WIDTH
8
PARAMETER_SIGNED_DEC
USR
LPM_DIRECTION
RIGHT
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
SHIFTOUT
-1
3
SHIFTIN
-1
3
Q7
-1
3
Q6
-1
3
Q5
-1
3
Q4
-1
3
Q3
-1
3
Q2
-1
3
Q1
-1
3
Q0
-1
3
ENABLE
-1
3
CLOCK
-1
3
ACLR
-1
3
}
# include_file {
c:|altera|80|quartus|libraries|megafunctions|dffeea.inc
55d29d20f7e852c37746bec4e2495ec
c:|altera|80|quartus|libraries|megafunctions|aglobal80.inc
9274497d636e3ed37111b8c54bf938
c:|altera|80|quartus|libraries|megafunctions|lpm_constant.inc
dcde44eee59335c1e2fe75d574f9646
}
# macro_sequence

# end
# entity
altsyncram
# storage
db|dds.(15).cnf
db|dds.(15).cnf
# case_insensitive
# source_file
c:|altera|80|quartus|libraries|megafunctions|altsyncram.tdf
377de9a85d1ccfacb5bddd3c464c9087
6
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
37
PARAMETER_SIGNED_DEC
USR
WIDTHAD_A
8
PARAMETER_SIGNED_DEC
USR
NUMWORDS_A
0
PARAMETER_SIGNED_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WIDTH_B
37
PARAMETER_SIGNED_DEC
USR
WIDTHAD_B
8
PARAMETER_SIGNED_DEC
USR
NUMWORDS_B
0
PARAMETER_SIGNED_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
WIDTH_BYTEENA_A
1
PARAMETER_SIGNED_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_SIGNED_DEC
USR
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_SIGNED_DEC
USR
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
USR
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
USR
INIT_FILE
UNUSED
PARAMETER_UNKNOWN
DEF
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
USR
MAXIMUM_DEPTH
0
PARAMETER_SIGNED_DEC
USR
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
USR
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
USR
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_05p3
PARAMETER_UNKNOWN
USR
}
# used_port {
wren_a
-1
3
q_b9
-1
3
q_b8
-1
3
q_b7
-1
3
q_b6
-1
3
q_b5
-1
3
q_b4
-1
3
q_b36
-1
3
q_b35
-1
3
q_b34
-1
3
q_b33
-1
3
q_b32
-1
3
q_b31
-1
3
q_b30
-1
3
q_b3
-1
3
q_b29
-1
3
q_b28
-1
3
q_b27
-1
3
q_b26
-1
3
q_b25
-1
3
q_b24
-1
3
q_b23
-1
3
q_b22
-1
3
q_b21
-1
3
q_b20
-1
3
q_b2
-1
3
q_b19
-1
3
q_b18
-1
3
q_b17
-1