prev_cmp_dds.tan.qmsg

FPGA实现DDS

{ "Info" "ITDB_FULL_TPD_RESULT" "FCW\[1\] altera_auto_signaltap_0_FCW\[1\]_ae 9.903 ns Longest " "Info: Longest tpd from source pin \"FCW\[1\]\" to destination pin \"altera_auto_signaltap_0_FCW\[1\]_ae\" is 9.903 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.014 ns) 1.014 ns FCW\[1\] 1 PIN PIN_207 4 " "Info: 1: + IC(0.000 ns) + CELL(1.014 ns) = 1.014 ns; Loc. = PIN_207; Fanout = 4; PIN Node = 'FCW\[1\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { FCW[1] } "NODE_NAME" } } { "dds.vhd" "" { Text "D:/dds/dds.vhd" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(7.089 ns) + CELL(0.319 ns) 8.422 ns altera_auto_signaltap_0_FCW\[1\]_signaltap_lcell 2 COMB LCCOMB_X14_Y9_N24 1 " "Info: 2: + IC(7.089 ns) + CELL(0.319 ns) = 8.422 ns; Loc. = LCCOMB_X14_Y9_N24; Fanout = 1; COMB Node = 'altera_auto_signaltap_0_FCW\[1\]_signaltap_lcell'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.408 ns" { FCW[1] altera_auto_signaltap_0_FCW[1]_signaltap_lcell } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.481 ns) + CELL(0.000 ns) 9.903 ns altera_auto_signaltap_0_FCW\[1\]_ae 3 PIN LCCOMB_X18_Y11_N22 0 " "Info: 3: + IC(1.481 ns) + CELL(0.000 ns) = 9.903 ns; Loc. = LCCOMB_X18_Y11_N22; Fanout = 0; PIN Node = 'altera_auto_signaltap_0_FCW\[1\]_ae'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.481 ns" { altera_auto_signaltap_0_FCW[1]_signaltap_lcell altera_auto_signaltap_0_FCW[1]_ae } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.333 ns ( 13.46 % ) " "Info: Total cell delay = 1.333 ns ( 13.46 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.570 ns ( 86.54 % ) " "Info: Total interconnect delay = 8.570 ns ( 86.54 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "9.903 ns" { FCW[1] altera_auto_signaltap_0_FCW[1]_signaltap_lcell altera_auto_signaltap_0_FCW[1]_ae } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "9.903 ns" { FCW[1] {} FCW[1]~combout {} altera_auto_signaltap_0_FCW[1]_signaltap_lcell {} altera_auto_signaltap_0_FCW[1]_ae {} } { 0.000ns 0.000ns 7.089ns 1.481ns } { 0.000ns 1.014ns 0.319ns 0.000ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 0}
{ "Info" "ITDB_TH_RESULT" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|lpm_shiftreg:trigger_condition_deserialize\|dffs\[110\] altera_internal_jtag~TDIUTAP altera_internal_jtag~TCKUTAP 1.850 ns register " "Info: th for register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|lpm_shiftreg:trigger_condition_deserialize\|dffs\[110\]\" (data pin = \"altera_internal_jtag~TDIUTAP\", clock pin = \"altera_internal_jtag~TCKUTAP\") is 1.850 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 5.306 ns + Longest register " "Info: + Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 5.306 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y7_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y7_N0; Fanout = 1; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.812 ns) + CELL(0.000 ns) 3.812 ns altera_internal_jtag~TCKUTAPclkctrl 2 COMB CLKCTRL_G0 581 " "Info: 2: + IC(3.812 ns) + CELL(0.000 ns) = 3.812 ns; Loc. = CLKCTRL_G0; Fanout = 581; COMB Node = 'altera_internal_jtag~TCKUTAPclkctrl'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.812 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.828 ns) + CELL(0.666 ns) 5.306 ns sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|lpm_shiftreg:trigger_condition_deserialize\|dffs\[110\] 3 REG LCFF_X15_Y8_N9 3 " "Info: 3: + IC(0.828 ns) + CELL(0.666 ns) = 5.306 ns; Loc. = LCFF_X15_Y8_N9; Fanout = 3; REG Node = 'sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_basic_multi_level_trigger:\\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm\|lpm_shiftreg:trigger_condition_deserialize\|dffs\[110\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.494 ns" { altera_internal_jtag~TCKUTAPclkctrl sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[110] } "NODE_NAME" } } { "LPM_SHIFTREG.tdf" "" { Text "c:/altera/80/quartus/libraries/megafunctions/LPM_SHIFTREG.tdf" 56 7 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.666 ns ( 12.55 % ) " "Info: Total cell delay = 0.666 ns ( 1