prev_cmp_dds.tan.qmsg

FPGA实现DDS

{ "Info" "ITDB_TSU_RESULT" "sync_fcw\[7\] FCW\[7\] SYSCLK 6.663 ns register " "Info: tsu for register \"sync_fcw\[7\]\" (data pin = \"FCW\[7\]\", clock pin = \"SYSCLK\") is 6.663 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.505 ns + Longest pin register " "Info: + Longest pin to register delay is 9.505 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.994 ns) 0.994 ns FCW\[7\] 1 PIN PIN_199 4 " "Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_199; Fanout = 4; PIN Node = 'FCW\[7\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { FCW[7] } "NODE_NAME" } } { "dds.vhd" "" { Text "D:/dds/dds.vhd" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(7.814 ns) + CELL(0.589 ns) 9.397 ns sync_fcw~292 2 COMB LCCOMB_X12_Y11_N10 1 " "Info: 2: + IC(7.814 ns) + CELL(0.589 ns) = 9.397 ns; Loc. = LCCOMB_X12_Y11_N10; Fanout = 1; COMB Node = 'sync_fcw~292'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "8.403 ns" { FCW[7] sync_fcw~292 } "NODE_NAME" } } { "dds.vhd" "" { Text "D:/dds/dds.vhd" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 9.505 ns sync_fcw\[7\] 3 REG LCFF_X12_Y11_N11 2 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 9.505 ns; Loc. = LCFF_X12_Y11_N11; Fanout = 2; REG Node = 'sync_fcw\[7\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { sync_fcw~292 sync_fcw[7] } "NODE_NAME" } } { "dds.vhd" "" { Text "D:/dds/dds.vhd" 102 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.691 ns ( 17.79 % ) " "Info: Total cell delay = 1.691 ns ( 17.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.814 ns ( 82.21 % ) " "Info: Total interconnect delay = 7.814 ns ( 82.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "9.505 ns" { FCW[7] sync_fcw~292 sync_fcw[7] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "9.505 ns" { FCW[7] {} FCW[7]~combout {} sync_fcw~292 {} sync_fcw[7] {} } { 0.000ns 0.000ns 7.814ns 0.000ns } { 0.000ns 0.994ns 0.589ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "dds.vhd" "" { Text "D:/dds/dds.vhd" 102 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SYSCLK destination 2.802 ns - Shortest register " "Info: - Shortest clock path from clock \"SYSCLK\" to destination register is 2.802 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns SYSCLK 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'SYSCLK'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { SYSCLK } "NODE_NAME" } } { "dds.vhd" "" { Text "D:/dds/dds.vhd" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns SYSCLK~clkctrl 2 COMB CLKCTRL_G2 791 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 791; COMB Node = 'SYSCLK~clkctrl'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { SYSCLK SYSCLK~clkctrl } "NODE_NAME" } } { "dds.vhd" "" { Text "D:/dds/dds.vhd" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.853 ns) + CELL(0.666 ns) 2.802 ns sync_fcw\[7\] 3 REG LCFF_X12_Y11_N11 2 " "Info: 3: + IC(0.853 ns) + CELL(0.666 ns) = 2.802 ns; Loc. = LCFF_X12_Y11_N11; Fanout = 2; REG Node = 'sync_fcw\[7\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.519 ns" { SYSCLK~clkctrl sync_fcw[7] } "NODE_NAME" } } { "dds.vhd" "" { Text "D:/dds/dds.vhd" 102 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 64.45 % ) " "Info: Total cell delay = 1.806 ns ( 64.45 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.996 ns ( 35.55 % ) " "Info: Total interconnect delay = 0.996 ns ( 35.55 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.802 ns" { SYSCLK SYSCLK~clkctrl sync_fcw[7] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.802 ns" { SYSCLK {} SYSCLK~combout {} SYSCLK~clkctrl {} sync_fcw[7] {} } { 0.000ns 0.000ns 0.143ns 0.853ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "9.505 ns" { FCW[7] sync_fcw~292 sync_fcw[7] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "9.505 ns" { FCW[7] {} FCW[7]~combout {} sync_fcw~292 {} sync_fcw[7] {} } { 0.000ns 0.000ns 7.814ns 0.000ns } { 0.000ns 0.994ns 0.589ns 0.108ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.802 ns" { SYSCLK SYSCLK~clkctrl sync_fcw[7] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.802 ns" { SYSCLK {} SYSCLK~combout {} SYSCLK~clkctrl {} sync_fcw[7] {} } { 0.000ns 0.000ns 0.143ns 0.853ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "SYSCLK SIN_OUT\[9\] SIN_OUT\[9\]~reg0 9.655 ns register " "Info: tco from clock \"SYSCLK\" to destination pin \"SIN_OUT\[9\]\" through register \"SIN_OUT\[9\]~reg0\" is 9.655 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SYSCLK source 2.764 ns + Longest register " "Info: + Longest clock path from clock \"SYSCLK\" to source register is 2.764 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns SYSCLK 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'SYSCLK'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { SYSCLK } "NODE_NAME" } } { "dds.vhd" "" { Text "D:/dds/dds.vhd" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns SYSCLK~clkctrl 2 COMB CLKCTRL_G2 791 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 791; COMB Node = 'SYSCLK~clkctrl'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { SYSCLK SYSCLK~clkctrl } "NODE_NAME" } } { "dds.vhd" "" { Text "D:/dds/dds.vhd" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.815 ns) + CELL(0.666 ns) 2.764 ns SIN_OUT\[9\]~reg0 3 REG LCFF_X12_Y7_N31 4 " "Info: 3: + IC(0.815 ns) + CELL(0.666 ns) = 2.764 ns; Loc. = LCFF_X12_Y7_N31; Fanout = 4; REG Node = 'SIN_OUT\[9\]~reg0'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.481 ns" { SYSCLK~clkctrl SIN_OUT[9]~reg0 } "NODE_NAME" } } { "dds.vhd" "" { Text "D:/dds/dds.vhd" 173 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 65.34 % ) " "Info: Total cell delay = 1.806 ns ( 65.34 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.958 ns ( 34.66 % ) " "Info: Total interconnect delay = 0.958 ns ( 34.66 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.764 ns" { SYSCLK SYSCLK~clkctrl SIN_OUT[9]~reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.764 ns" { SYSCLK {} SYSCLK~combout {} SYSCLK~clkctrl {} SIN_OUT[9]~reg0 {} } { 0.000ns 0.000ns 0.143ns 0.815ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "dds.vhd" "" { Text "D:/dds/dds.vhd" 173 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.587 ns + Longest register pin " "Info: + Longest register to pin delay is 6.587 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns SIN_OUT\[9\]~reg0 1 REG LCFF_X12_Y7_N31 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X12_Y7_N31; Fanout = 4; REG Node = 'SIN_OUT\[9\]~reg0'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { SIN_OUT[9]~reg0 } "NODE_NAME" } } { "dds.vhd" "" { Text "D:/dds/dds.vhd" 173 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.481 ns) + CELL(3.106 ns) 6.587 ns SIN_OUT\[9\] 2 PIN PIN_120 0 " "Info: 2: + IC(3.481 ns) + CELL(3.106 ns) = 6.587 ns; Loc. = PIN_120; Fanout = 0; PIN Node = 'SIN_OUT\[9\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.587 ns" { SIN_OUT[9]~reg0 SIN_OUT[9] } "NODE_NAME" } } { "dds.vhd" "" { Text "D:/dds/dds.vhd" 173 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.106 ns ( 47.15 % ) " "Info: Total cell delay = 3.106 ns ( 47.15 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.481 ns ( 52.85 % ) " "Info: Total interconnect delay = 3.481 ns ( 52.85 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.587 ns" { SIN_OUT[9]~reg0 SIN_OUT[9] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.587 ns" { SIN_OUT[9]~reg0 {} SIN_OUT[9] {} } { 0.000ns 3.481ns } { 0.000ns 3.106ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.764 ns" { SYSCLK SYSCLK~clkctrl SIN_OUT[9]~reg0 } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.764 ns" { SYSCLK {} SYSCLK~combout {} SYSCLK~clkctrl {} SIN_OUT[9]~reg0 {} } { 0.000ns 0.000ns 0.143ns 0.815ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.587 ns" { SIN_OUT[9]~reg0 SIN_OUT[9] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.587 ns" { SIN_OUT[9]~reg0 {} SIN_OUT[9] {} } { 0.000ns 3.481ns } { 0.000ns 3.106ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 0}