stp1.stp

FPGA实现DDS

          <wire name="SIN_OUT[11]" tap_mode="classic" type="output pin"/>
          <wire name="SIN_OUT[12]" tap_mode="classic" type="output pin"/>
          <wire name="SIN_OUT[13]" tap_mode="classic" type="output pin"/>
          <wire name="SIN_OUT[1]" tap_mode="classic" type="output pin"/>
          <wire name="SIN_OUT[2]" tap_mode="classic" type="output pin"/>
          <wire name="SIN_OUT[3]" tap_mode="classic" type="output pin"/>
          <wire name="SIN_OUT[4]" tap_mode="classic" type="output pin"/>
          <wire name="SIN_OUT[5]" tap_mode="classic" type="output pin"/>
          <wire name="SIN_OUT[6]" tap_mode="classic" type="output pin"/>
          <wire name="SIN_OUT[7]" tap_mode="classic" type="output pin"/>
          <wire name="SIN_OUT[8]" tap_mode="classic" type="output pin"/>
          <wire name="SIN_OUT[9]" tap_mode="classic" type="output pin"/>
        </data_input_vec>
      </signal_vec>
      <presentation>
        <data_view>
          <bus is_signal_inverted="no" link="all" name="SIN_OUT" order="lsb_to_msb" radix="line" state="collapse" type="output pin">
            <net is_signal_inverted="no" name="SIN_OUT[0]"/>
            <net is_signal_inverted="no" name="SIN_OUT[1]"/>
            <net is_signal_inverted="no" name="SIN_OUT[2]"/>
            <net is_signal_inverted="no" name="SIN_OUT[3]"/>
            <net is_signal_inverted="no" name="SIN_OUT[4]"/>
            <net is_signal_inverted="no" name="SIN_OUT[5]"/>
            <net is_signal_inverted="no" name="SIN_OUT[6]"/>
            <net is_signal_inverted="no" name="SIN_OUT[7]"/>
            <net is_signal_inverted="no" name="SIN_OUT[8]"/>
            <net is_signal_inverted="no" name="SIN_OUT[9]"/>
            <net is_signal_inverted="no" name="SIN_OUT[10]"/>
            <net is_signal_inverted="no" name="SIN_OUT[11]"/>
            <net is_signal_inverted="no" name="SIN_OUT[12]"/>
            <net is_signal_inverted="no" name="SIN_OUT[13]"/>
          </bus>
          <net is_signal_inverted="no" name="NCLR"/>
          <bus is_signal_inverted="no" link="all" name="FCW" order="lsb_to_msb" radix="hex" state="collapse" type="input pin">
            <net is_signal_inverted="no" name="FCW[0]"/>
            <net is_signal_inverted="no" name="FCW[1]"/>
            <net is_signal_inverted="no" name="FCW[2]"/>
            <net is_signal_inverted="no" name="FCW[3]"/>