dds.tan.summary

FPGA实现DDS

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 6.321 ns
From           : FCW[4]
To             : sync_fcw[4]
From Clock     : --
To Clock       : SYSCLK
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 9.082 ns
From           : SIN_OUT[9]~reg0
To             : SIN_OUT[9]
From Clock     : SYSCLK
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -4.473 ns
From           : FCW[8]
To             : sync_fcw[8]
From Clock     : --
To Clock       : SYSCLK
Failed Paths   : 0

Type           : Clock Setup: 'SYSCLK'
Slack          : N/A
Required Time  : None
Actual Time    : 170.71 MHz ( period = 5.858 ns )
From           : altsyncram:sin_rom|altsyncram_5h11:auto_generated|ram_block1a0~porta_address_reg8
To             : SIN_OUT[6]~reg0
From Clock     : SYSCLK
To Clock       : SYSCLK
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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