dds.vhd.bak

FPGA实现DDS

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    01:50:07 10/15/2008 
-- Design Name: 
-- Module Name:    dds.vhd - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: DDS合成器，参考多个文件修改
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;

entity dds is
  generic(
    FCW_WIDTH : positive := 22;  	--频率控制字位数
    ROM_WIDTH : positive :=13;		--ROM里面正弦表的宽度
    ROM_WIDTHAD : positive :=9;		--ROM中地址的位数	
    SIN_ROM_FILE : string :="sin.mif"   --ROM的地址
    COS_ROM_FILE : string :="cos.mif"   
    );			
  port (
    SYSCLK : in STD_LOGIC :='0';	--系统输入时钟  50M
    NCLR : in std_logic :='0';		--复位信号，低电平复位
    FCW : in STD_LOGIC_vector(FCW_WIDTH-1 downto 0);  --频率控制字，22位
    SIN_OUT : out STD_LOGIC_vector(ROM_WIDTH downto 0)  --14单极性调制信号输出，给DA
    COS_OUT : out STD_LOGIC_vector(ROM_WIDTH downto 0) 
    );
end dds;


architecture Behavioral of dds is	
  signal acc_adder : std_logic_vector(FCW_WIDTH-1 downto 0);
  signal address : std_logic_vector(ROM_WIDTHAD-1 downto 0);
  signal sin_sign: std_logic;
  signal delay_sin_sign : std_logic;
  signal delay_cos_sign : std_logic;
  signal sync_fcw : std_logic_vector(FCW_WIDTH-1 downto 0);
  signal sin_rom_out : std_logic_vector(ROM_WIDTH-1 downto 0);
  signal cos_rom_out : std_logic_vector(ROM_WIDTH-1 downto 0);




COMPONENT altsyncram
	GENERIC (
		intended_device_family		: STRING;
		width_a		: NATURAL;
		widthad_a		: NATURAL;
		numwords_a		: NATURAL;
		operation_mode		: STRING;
		outdata_reg_a		: STRING;
		address_aclr_a		: STRING;
		outdata_aclr_a		: STRING;
		width_byteena_a		: NATURAL;
		init_file		: STRING;
		lpm_type		: STRING
	);
	PORT (
			clock0	: IN STD_LOGIC ;
			address_a	: IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0);
			q_a	: OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
			q_b : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0)
	);
end COMPONENT;
begin

  	sin_rom: altsyncram
	GENERIC map(
		intended_device_family => "cyclone",
		width_a => 13,
		widthad_a => 9,
		numwords_a => 512,
		operation_mode => "ROM",
		outdata_reg_a => "UNREGISTERED",
		address_aclr_a => "NONE",
		outdata_aclr_a => "NONE",
		width_byteena_a => 1,
		init_file => sin_rom_file,
		init1_file=> cos_rom_file,
		lpm_type => "altsyncram")
	PORT map(
			clock0=>SYSCLK,
			address_a=>address,
			q_a	=>sin_rom_out,
			q_b=>cos_rom_out	);

  -----------------------------------------------------------------------------
  -- 产生同步频率字
  -----------------------------------------------------------------------------
  PROCESS(SYSCLK, NCLR, FCW)
  begin
    if(SYSCLK'event and SYSCLK = '1')then
      if(NCLR='0') then	
		sync_fcw <= (others=>'0');		
      else
        sync_fcw <= FCW;				
      end if;
    end if;
  end process;
  -----------------------------------------------------------------------------
  -- 频率字累加 
  -----------------------------------------------------------------------------
  process(SYSCLK, NCLR, sync_fcw)
  begin
    if(SYSCLK'event and SYSCLK = '1')then
      if(NCLR='0') then	
		acc_adder <= (others=>'0');		
      else
        acc_adder <= acc_adder + sync_fcw;				
      end if;
    end if;
  end process;

  -----------------------------------------------------------------------------
  -- 根据频率字累加结果选择相应ROM地址地址
  -----------------------------------------------------------------------------
  process(SYSCLK,NCLR,address,sin_rom_out,cos_rom_out)			   
    variable temp_sign : std_logic_vector(1 downto 0);
  begin	
    if(SYSCLK'event and SYSCLK = '1')then
      if(NCLR='0') then
        address <= (others=>'0');
        sin_sign <= '0';
        cos_sign<='0';
      else
        temp_sign := acc_adder(fcw_width-1 downto fcw_width-2);
        if (temp_sign = "00") then						--first sphere
          address <= acc_adder(fcw_width-3 downto fcw_width-2-rom_widthad);
          sin_sign <= '0';
          cos_sign<='0';
        elsif (temp_sign = "01") then
          address <=not acc_adder(fcw_width-3 downto fcw_width-2-rom_widthad);
          sin_sign <= '0';
          cos_sign <= '1';
        elsif (temp_sign = "10") then					--third sphere
          address <=acc_adder(fcw_width-3 downto fcw_width-2-rom_widthad);				
          sin_sign <= '1';
          cos_sign <= '1';
        else								--fourth sphere
          address <=not acc_adder(fcw_width-3 downto fcw_width-2-rom_widthad);				
          sin_sign <= '1';
          cos_sign <= '0';
        end if;
      end if;
    end if;
  end process;

  -----------------------------------------------------------------------------
  -- 缓存符号位 
  -----------------------------------------------------------------------------
  process(SYSCLK, sin_sign,cos_sign)			   
  begin	
    if(SYSCLK'event and SYSCLK = '1')then
      if(NCLR='0') then
        delay_sin_sign <= '0';
      else
        delay_sin_sign <= sin_sign;
        delay_cos_sign <= cos_sign;
      end if;
    end if;
  end process;

  -----------------------------------------------------------------------------
  -- 输出单极性，14位有效数据，给DA
  -----------------------------------------------------------------------------
  process(SYSCLK, sin_sign,cos_sign, sin_rom_out)
    variable temp_sin : std_logic_vector(rom_width downto 0);
    variable temp_cos :	std_logic_vector(rom_width downto 0);	   
  begin	
    if(SYSCLK'event and SYSCLK = '1')then
	
      if(delay_sin_sign='0') then
		temp_sin(rom_width) := '1';
		temp_sin(rom_width-1 downto 0) := sin_rom_out;

      else			
		temp_sin(rom_width-1 downto 0) := not sin_rom_out;
		temp_sin(rom_width) := '0';

      end if;
    SIN_OUT <= temp_sin;
    end if;
  end process;		

end Behavioral;