initgen.vhd

来自「Actel Fusion System Management Developme」· VHDL 代码 · 共 133 行

-- ********************************************************************/ 
-- Copyright 2007 Actel Corporation.  All rights reserved.
-- IP Engineering 
--
-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN 
-- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED 
-- IN ADVANCE IN WRITING.  
--  
-- File:  initgen.vhd
--     
-- Description: Simple APB Bus Controller
--              Test Bench, initialisation stream generator  
--
-- Rev: 2.3   01Mar07 IPB  : Production Release   
--
-- Notes:
--
-- *********************************************************************/ 

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

use work.misc.all;
use work.textio.all;
use work.support.all;
use std.textio.all;


entity INITGEN is
  generic ( ENABLE    : boolean;
            ID        : integer range 0 to 9 ;
            AWIDTH    : integer range 1 to 16;  
            DWIDTH    : integer range 8 to 32;   
            SDEPTH    : integer range 1 to 16;    
            ICWIDTH   : integer range 1 to 16;
			INITWIDTH : integer range 1 to 16  
           );
  port ( PCLK        : in  std_logic;
         PRESETN     : in  std_logic;

         -- RAM Initialization Port
         INITDATVAL  : out std_logic;
         INITDONE    : out std_logic; 
         INITADDR    : out std_logic_vector(INITWIDTH-1 downto 0);
         INITDATA    : out std_logic_vector(8 downto 0)
        );
end INITGEN;



architecture RTL of INITGEN is

constant AW : integer := AWIDTH;
constant DW : integer := DWIDTH;
constant SW : integer := calc_swidth(SDEPTH);
constant RAMDEPTH : integer := 2**ICWIDTH;
constant RAMWIDTH : integer := AW+DW+SW+6;
constant NROWS    : integer := 1+ (RAMDEPTH-1)/512 ;
constant NCOLS    : integer := 1+ (RAMWIDTH-1)/9 ;
constant NRAMS    : integer := NCOLS*NROWS ;
constant RIDEPTH  : integer := NRAMS*512;
constant RIWIDTH  : integer := INITWIDTH;

begin
    
    
 process                                                                                                   
 file     FSTR        : TEXT;                                                                              
 variable L           : LINE;                                                                              
 variable filename    : string(1 to 12);                                                                   
 variable FSTATUS     : FILE_OPEN_STATUS;                                                                  
 variable ch    : character;                                                                               
 variable data : std_logic_vector(8 downto 0);                                                             
 begin                                                                                                     
   INITDATVAL <= '0';                                                                        
   INITDONE   <= '0';                                                                                     
   INITADDR   <= ( others => '0');                                                                        
   INITDATA   <= ( others => '0');                                                                        
   if not ENABLE then                                                                                      
     INITDONE  <= '1';                                                                                   
     wait;                                                                                                 
   end if;                                                                                                 
   wait until PRESETN='1';                                                                                 
   for i in 0 to 30 loop                                                                                   
     wait until PCLK='0';                                                                                  
   end loop;                                                                                               
   wait for (10 * 2**ICWIDTH) * 1 ns;                                                                      
   wait until PCLK='0';  
                                                                                     
   printf("Initialising Instruction RAMS through External Interface");                                     
   printf(" RAM size %d x 9",fmt(RIDEPTH));
                                                                                                           
   filename :=  "RAMABC_" & CHARACTER'VAL(ID+48) & ".mem"; 
   printf("  Loading RAM  %s",fmt(filename));                          
   file_open(fstatus,FSTR,filename);                                                                   
                                                                                                          
   for i in 0 to RIDEPTH-1 loop                                                                              
     readline(FSTR,L);                                                                                
     data := ( others => '0');                                                                         
     for b in 8 downto 0 loop                                                                          
        read(L,ch);                                                                                     
        case ch is                                                                                      
         when '0' => data(b) := '0';                                                                   
         when '1' => data(b) := '1';                                                                   
         when others => assert FALSE report "Illegal Character in Memory File" severity FAILURE;       
       end case;                                                                                       
     end loop;                                                                                         
     INITDATVAL <= '1';
	 INITADDR <= conv_std_logic_vector(i,RIWIDTH);                                                           
     INITDATA <= data;                                                                                 
     wait until PCLK='0';
	 -- Put some unknowns out to check strobes
     INITDATVAL <= '0';
     INITDATA   <= ( others => 'X');                                                                                 
     wait until PCLK='0';
	                                                                               
   end loop;                                                                                           
   INITDATVAL <= '0';
   file_close(FSTR);                                                                                   

   wait until PCLK='0';                                                                                     
   wait until PCLK='0';                                                                                     
   printf("Memory Initialisation Complete ");                                                               
   printf(" ");                                                                                             
   INITDONE  <= '1';                                                                                   
   wait;                                                                                                    
 end process;                                                                                             
    
    
    
end RTL;