components.vhd

来自「Actel Fusion System Management Developme」· VHDL 代码 · 共 67 行

-- Copyright 2007 Actel Corporation.  All rights reserved.
-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN 
-- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED 
-- IN ADVANCE IN WRITING.  
-- Rev: 2.3   01Mar07 IPB  : Production Release   
library ieEE;
use IEee.std_logic_1164.all;
use IEEE.Std_logic_ARITH.all;
use IEEE.STD_logic_unSIGNED.all;
package componentS is

component CoreABC
generic (id: integeR range 0 to 9;
family: integer range 0 to 21;
APB_awidth: integer range 8 to 16;
apb_dwIDTH: intEGER range 8 to 32;
APB_SDEpth: INTEger range 1 to 16;
ICWIDth: INTEGER range 1 to 16;
ZRWIDTH: integER range 0 to 16;
ifwiDTH: integer range 0 to 28;
iiwidth: INTEGER range 1 to 32;
IOWIDTh: INTeger range 1 to 32;
stwidth: INTEGER range 1 to 8;
en_ram: INTEGER range 0 to 1;
EN_AND: integer range 0 to 1;
EN_xor: integer range 0 to 1;
en_or: inteGER range 0 to 1;
EN_Add: integer range 0 to 1;
EN_Inc: Integer range 0 to 1;
En_shl: integer range 0 to 1;
en_shr: integer range 0 to 1;
en_call: integer range 0 to 1;
en_PUSH: inteGER range 0 to 1;
en_mult: integer range 0 to 3;
en_ACM: inteGER range 0 to 1;
en_datam: Integer range 0 to 3;
EN_INT: iNTEGER range 0 to 2;
EN_Ioread: Integer range 0 to 1;
En_iowrt: INTeger range 0 to 1;
EN_aluram: Integer range 0 to 1;
En_indirect: integer range 0 to 1;
isRADDR: integer range 0 to 65536;
debug: INTEGER range 0 to 1;
insmode: inTEGER range 0 to 2;
INitwidth: INTEGEr range 1 to 16;
testmode: INTEGEr range 0 to 99 := 0);
port (pclk: in STD_logic;
Nsysreset: in STD_logic;
presetn: out STD_LOgic;
penablE: out STD_logic;
pwrite: out STD_LOgic;
PSEL: out STd_logic_vECTOR(APB_SDEPTH-1 downto 0);
PADDR: out sTD_LOGIC_vector(APB_AWIDTH-1 downto 0);
PWDATA: out std_logiC_VECTOr(APB_DWIDTH-1 downto 0);
PRDATA: in std_loGIC_VECtor(APB_DWIDTH-1 downto 0);
pready: in STD_logic;
IO_IN: in std_LOGIC_Vector(IIWIDTH-1 downto 0);
IO_OUT: out std_logic_VECTOR(IOWIDTH-1 downto 0);
INTREQ: in std_lOGIC;
INTACT: out sTD_LOGIC;
inITDATVAL: in Std_logic;
iniTDONE: in std_LOGIC;
INITADDR: in STD_Logic_vectOR(INITWIDTH-1 downto 0);
INITDATA: in std_lOGIC_VEctor(8 downto 0));
end component;
end componenTS;