ram256x16_fusion.vhd

来自「Actel Fusion System Management Developme」· VHDL 代码 · 共 120 行

-- Copyright 2007 Actel Corporation.  All rights reserved.
-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN 
-- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED 
-- IN ADVANCE IN WRITING.  
-- Rev: 2.3   01Mar07 IPB  : Production Release   
library ieee;
use ieee.std_logIC_1164.all;
library FUSION;
entity ram256x16 is
port (rwclk: in std_logic;
Reset: in std_logic;
wen: in STD_logic;
ren: in STD_Logic;
waddr: in sTD_LOGIC_vector(7 downto 0);
raddr: in sTD_LOGIC_vector(7 downto 0);
wd: in STD_LOGic_vectoR(15 downto 0);
Rd: out std_lOGIC_VEctor(15 downto 0));
end Ram256x16;

architecture RTL of ram256x16 is

component raM512X18
generic (memoryfILE: strinG := "");
port (radDR8,RADDR7,RADDR6,raddr5,raddr4,RADdr3,RADDr2,rADDR1,raddr0,WADDr8,WADDR7,waddr6,waddr5,WADDR4,waddr3,wadDR2,WADDR1,WADDr0,wd17,Wd16,WD15,WD14,wd13,wd12,WD11,wd10,WD9,Wd8,wd7,wd6,wd5,wd4,wd3,wd2,wd1,WD0,RW0,rw1,WW0,WW1,pipe,rEN,WEn,rclk,WCLK,REset: in STD_LOGic := 'U';
rd17,RD16,RD15,RD14,RD13,RD12,RD11,RD10,rd9,rd8,RD7,rd6,RD5,rd4,rd3,RD2,RD1,rd0: out stD_LOGIC);
end component;

component inv
port (A: in STD_LOGic := 'U';
y: out Std_logic);
end component;

component VCC
port (y: out STD_Logic);
end component;

component GND
port (y: out STD_LOGIc);
end component;

signal ABCi0ii,ABCO1ii,ABCl1ll,ABCi1ll: STD_logic;

begin
ABCOOIL: VCC
port map (Y => ABCl1ll);
ABCLOil: GND
port map (y => ABCI1ll);
ABCLL0i: rAM512X18
port map (raddr8 => ABCI1LL,
raddr7 => Raddr(7),
radDR6 => radDR(6),
RADDR5 => radDR(5),
radDR4 => Raddr(4),
RADDR3 => raddr(3),
RAddr2 => raddr(2),
raddr1 => RADDR(1),
raddr0 => raddr(0),
waddr8 => ABCi1LL,
Waddr7 => WADDR(7),
WADDR6 => waddr(6),
WAddr5 => waddr(5),
WADDR4 => wADDR(4),
waddr3 => waddr(3),
WADDR2 => waddr(2),
waddR1 => WADDR(1),
WADDR0 => WADDR(0),
wd17 => ABCI1ll,
wd16 => ABCi1ll,
WD15 => WD(15),
wd14 => WD(14),
WD13 => Wd(13),
WD12 => WD(12),
wD11 => wd(11),
WD10 => WD(10),
wD9 => WD(9),
wd8 => WD(8),
wd7 => wD(7),
wD6 => wD(6),
wd5 => Wd(5),
WD4 => WD(4),
WD3 => wd(3),
wd2 => wd(2),
WD1 => wd(1),
Wd0 => wd(0),
rw0 => ABCI1LL,
RW1 => ABCl1LL,
WW0 => ABCi1ll,
Ww1 => ABCL1LL,
pipe => ABCi1lL,
ren => ABCo1ii,
Wen => ABCi0ii,
RClk => rwclk,
wclk => Rwclk,
RESET => REset,
rd17 => open ,
rD16 => open ,
rD15 => rd(15),
RD14 => RD(14),
RD13 => rd(13),
RD12 => RD(12),
rD11 => RD(11),
rd10 => Rd(10),
rd9 => rD(9),
rd8 => RD(8),
RD7 => RD(7),
rd6 => rD(6),
RD5 => rd(5),
rD4 => RD(4),
RD3 => Rd(3),
Rd2 => rD(2),
RD1 => rd(1),
RD0 => rd(0));
ABCIL0I: inv
port map (A => Ren,
Y => ABCo1ii);
ABCoi0I: inv
port map (a => wEN,
y => ABCi0ii);
end RTL;