support.vhd

来自「Actel Fusion System Management Developme」· VHDL 代码 · 共 1,447 行 · 第 1/3 页

-- Copyright 2007 Actel Corporation.  All rights reserved.
-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN 
-- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED 
-- IN ADVANCE IN WRITING.  
-- Rev: 2.3   01Mar07 IPB  : Production Release   
library ieee;
use ieee.STD_LOGIC_1164.all;
use IEEE.std_loGIC_ARIth.all;
use IEEE.STD_logic_unsIGNED.all;
package support is

function cleAN(X: std_logic_VECTOR)
return std_lOGIC_VEctor;

function ABCi01i(ABCO11i,ABCl11i,ABCi11i,ABCooo0,ABCloo0: std_loGIC_VECtor)
return sTD_LOGIC_vector;

function ABCll1(ABCIOO0: integER)
return Std_logic;

function ABCll1(ABCIOO0: booLEAN)
return STD_logic;

function log2R(X: inTEGER)
return INTeger;

function ABCOlo0(EN_RAM,EN_CALL,DWIDTH,ICWIDTH: INteger)
return integer;

function CALC_SWidth(x: inTEGER)
return integer;

function Calc_initwIDTH(awidth,dWIDTH,ABCllo0,ICWIDTH: Integer)
return integer;

function Max(A,B: INteger)
return INTEGer;

function mIN(A,b: integer)
return Integer;

function ABCILO0(ABCoio0: INTEGER;
s1: INTEGER;
ABCLIO0: intEGER;
ABCIIO0: inTEGER;
ABCO0o0: INTEGER;
ABCl0o0: INTEGEr)
return std_logic_VECTOR;

function doins(S1: INteger)
return STD_LOgic_vectoR;

function Doins(s1: inTEGER;
ABCLIO0: intEGER)
return STD_LOgic_vectoR;

function doins(s1: integer;
ABClio0: iNTEGER;
ABCiio0: integER)
return std_loGIC_VECtor;

function DOINS(s1: integer;
ABClio0: iNTEGER;
ABCiio0: integeR;
ABCO0o0: integer)
return std_lOGIC_VEctor;

function DOINS(S1: integer;
ABClio0: inTEGER;
ABCiio0: intEGER;
ABCo0o0: integER;
ABCL0O0: integer)
return STD_logic_veCTOR;

function CHARtoint(C: characTER)
return Integer;

component ABCil0
generic (AWIDTH: intEGER range 1 to 16;
DWIDth: integer range 8 to 32;
swidth: integer range 0 to 4;
ICWIDTH: INTEGer range 1 to 16;
ABCoi0: integer range 1 to 65536;
iwwidTH: intEGER range 1 to 64;
INITWIDTH: integer range 1 to 16;
TESTMODE: INTEGEr range 0 to 99;
ID: integER range 0 to 25);
port (CLK: in STD_logic;
ABCLI0: in std_logiC;
initdatvaL: in Std_logic;
INitdone: in STD_LOgic;
INITADDR: in STD_Logic_vectOR(INITWIDTH-1 downto 0);
INITDATA: in STD_logic_veCTOR(8 downto 0);
ADDRESS: in STD_LOGIc_vector(ICWIDTH-1 downto 0);
instruCTION: out std_logic_VECTOR(iwWIDTH-1 downto 0));
end component;

component iNSTRUCTIOns
generic (awidth: integer range 1 to 16;
DWIDTH: INTEger range 8 to 32;
SWIdth: INteger range 0 to 4;
ICWidth: Integer range 1 to 16;
iiwiDTH: INTEger range 1 to 32;
ifwidtH: integer range 0 to 28;
IWWIDTH: INTEGER range 1 to 64;
eN_MULT: iNTEGER range 0 to 3;
EN_inc: INTEGER range 0 to 1;
iD: INTEGer range 0 to 9;
Testmode: iNTEGER range 0 to 99);
port (address: in STD_Logic_vectOR(ICWIDTH-1 downto 0);
INStruction: out std_LOGIC_vector(IWWIDTH-1 downto 0));
end component;

component ACMTABLe
generic (id: integer range 0 to 9;
tm: INTEGER range 0 to 99);
port (acmaddr: in STD_LOGic_vector(7 downto 0);
acmDATA: out Std_logic_vECTOR(7 downto 0);
ACMDO: out STD_Logic);
end component;

component ABCLI0I
generic (DWIDTH: integer range 8 to 32;
FAMILY: integeR range 0 to 21);
port (Clk: in Std_logic;
RESETN: in STd_logic;
weN: in std_logIC;
ADDR: in Std_logic_VECTOR(7 downto 0);
WD: in Std_logic_vECTOR(dwIDTH-1 downto 0);
RD: out STD_logic_vecTOR(dwidth-1 downto 0));
end component;

component ram256x8 is
port (RWCLK: in STD_logic;
RESET: in STD_logic;
weN: in std_LOGIC;
REN: in STD_Logic;
waddr: in std_loGIC_VECtor(7 downto 0);
Raddr: in STD_logic_vecTOR(7 downto 0);
wd: in std_LOGIC_VEctor(7 downto 0);
RD: out std_logiC_VECTOr(7 downto 0));
end component;

component RAM256x16 is
port (RWCLK: in std_logIC;
RESEt: in std_logic;
WEN: in std_LOGIC;
Ren: in STd_logic;
waddr: in std_logic_VECTOR(7 downto 0);
RADdr: in STD_LOGic_vector(7 downto 0);
wd: in STD_Logic_vectOR(15 downto 0);
RD: out std_logIC_VECTor(15 downto 0));
end component;

component ram128x32 is
port (rwclk: in std_LOGIC;
RESEt: in std_logic;
WEN: in STD_LOGic;
ren: in STD_LOGIc;
WADDR: in std_logIC_VECTor(6 downto 0);
rADDR: in STd_logic_veCTOR(6 downto 0);
wd: in STD_logic_vectOR(31 downto 0);
rd: out std_logic_VECTOR(31 downto 0));
end component;

component DEBUGBLK
generic (DEBUG: iNTEGER range 0 to 1;
awidTH: inteGER range 1 to 16;
DWIDTH: inTEGER range 8 to 32;
SWIDTH: inteGER range 0 to 4;
sDEPTH: integer range 1 to 16;
icwidtH: INTeger range 1 to 16;
icdEPTH: integer range 1 to 65536;
ZRWIDTH: integer range 0 to 16;
IIWidth: integER range 1 to 32;
iowidth: intEGER range 1 to 32;
irwidtH: INTEGER range 1 to 32;
en_MULT: INTeger range 0 to 3);
port (pclK: in std_loGIC;
resetn: in STD_LOGIc;
Isr: in std_logic;
SMADDr: in sTD_LOGIC_vector(ICWIDTH-1 downto 0);
INSTR_cmd: in STD_LOGIc_vector(2 downto 0);
INStr_scmd: in std_logiC_VECTOr(2 downto 0);
instr_datA: in STD_logic_vecTOR(dwidth-1 downto 0);
insTR_ADDR: in std_loGIC_VECtor(awidth-1 downto 0);
instr_sloT: in std_loGIC_VECtor(swidth downto 0);
PRDATA: in STD_logic_veCTOR(dwidth-1 downto 0);
PWDATA: in sTD_LOGIC_vector(Dwidth-1 downto 0);
ACCum_old: in std_LOGIC_Vector(DWIDTH-1 downto 0);
accum_new: in std_logiC_VECTOr(Dwidth-1 downto 0);
ACCUM_zero: in stD_LOGIC;
accum_neg: in std_LOGIC;
FLAGS: in STD_Logic;
ramDOUT: in std_logic_VECTOR(dwIDTH-1 downto 0);
STkptr: in std_LOGIC_vector(7 downto 0);
zregisTER: in std_LOGIC_Vector(ZRWIDTH downto 0);
ACMdo: in std_logiC;
deBUG1: in STD_LOGIc;
debuG2: in std_LOGIC);
end component;

component iram512X9
generic (ID: INTeger;
CID: integer;
rid: Integer);
port (RWCLk: in Std_logic;
reseT: in std_lOGIC;
renablE: in std_lOGIC;
RADDR: in STD_logic_vecTOR(8 downto 0);
rd: out std_lOGIC_VEctor(8 downto 0);
INITADDR: in STD_logic_vecTOR(8 downto 0);
wenabLE: in std_logic;
INITDATA: in std_lOGIC_VEctor(8 downto 0));
end component;

component ABCI01
generic (aWIDTH: INTeger range 1 to 16;
DWidth: integeR range 8 to 32;
swidth: intEGER range 0 to 4;
ICWIDTH: integER range 1 to 16;
ABCOI0: INTEGer range 1 to 65536;
IWWIDth: integer range 1 to 64;
id: Integer range 0 to 25);
port (CLK: in Std_logic;
ABCLI0: in std_loGIC;
ABCO11: in std_logic;
ABCl11: out STD_Logic;
ADdress: in stD_LOGIC_vector(ICWIDTH-1 downto 0);
instrUCTION: out std_logic_VECTOR(iwwidtH-1 downto 0));
end component;

constant BLAnk: INTEGer := -1;

constant inoP: integer := 256*1;

constant ILOAD: integeR := 256*2;

constant iINCB: integer := 256*3;

constant IAND: integer := 256*4;

constant ior: intEGER := 256*5;

constant IXor: intEGER := 256*6;

constant iADD: INTeger := 256*7;

constant ISub: integer := 256*8;

constant Ishl0: intEGER := 256*9;

constant ishl1: intEGER := 256*10;

constant ishle: iNTEGER := 256*11;

constant IROL: INTEger := 256*12;

constant IShr0: INteger := 256*13;

constant ishr1: INTEGER := 256*14;

constant Ishre: INteger := 256*15;

constant IROR: INTEGER := 256*16;

constant icmp: INTEger := 256*17;

constant iCMPLEQ: INTEGER := 256*18;

constant iBITCLR: iNTEGER := 256*19;

constant Ibitset: INteger := 256*20;

constant IBITTST: iNTEGER := 256*21;

constant iapbread: Integer := 256*22;

constant iapbWRT: integer := 256*23;

constant ILOAdz: INTEGER := 256*24;

constant IDECZ: intEGER := 256*25;

constant IINCZ: integer := 256*26;

constant iiowrt: Integer := 256*27;

constant IRAMREAd: iNTEGER := 256*28;

constant IRAMWRt: integeR := 256*29;

constant ipush: intEGER := 256*30;

constant ipop: inteGER := 256*31;

constant IIOREAD: Integer := 256*32;

constant IUSER: INTeger := 256*33;

constant IJUMPb: integer := 256*34;

constant Icallb: Integer := 256*35;

constant ireturnb: inteGER := 256*36;

constant IRETIsrb: integer := 256*37;

constant IWAITb: INTEger := 256*38;

constant IHALTB: iNTEGER := 256*38;

constant IMULT: inTEGER := 256*39;

constant idec: INTEger := 256*40;

constant IAPBReadz: INTEger := 256*41;

constant IAPBwrtz: INTEGer := 256*42;

constant Iaddz: INTEGEr := 256*43;

constant isubz: INTEGer := 256*44;

constant idat: INTEGER := 10;

constant IDat8: inTEGER := 11;

constant idAT16: integer := 12;

constant iDAT32: integer := 13;

constant IACM: integer := 14;

constant iaCC: INTEGer := 15;

constant irAM: INTEGER := 16;

constant ABCi0o0: INTeger := 10;

constant DAT8: integer := 11;

constant DAT16: integer := 12;

constant DAT32: integER := 13;

constant ACM: INTEGER := 14;

constant ACC: Integer := 15;

constant RAM: INTeger := 16;

constant iifnot: Integer := 0;

constant INOTif: INTEGER := 0;

constant Iif: iNTEGER := 1;

constant IUNTIL: inTEGER := 0;

constant inotunTIL: integeR := 1;

constant IUNTILnot: INTEGEr := 1;

constant iwhile: INTEGER := 1;

constant IZzero: INTEGER := 16#08#;

constant INEGAtive: INTEGEr := 16#04#;

constant IZEro: inteGER := 16#02#;

constant ILte_zero: INTEGer := 16#06#;

constant IALways: inTEGER := 16#01#;

constant IINPUT0: integer := 16#010#;

constant IInput1: integer := 16#020#;

constant Iinput2: inteGER := 16#040#;

constant IINPut3: integer := 16#080#;

constant iiNPUT4: INTEger := 16#100#;

constant IINPUt5: Integer := 16#200#;

constant IINPUT6: integer := 16#400#;

constant IINPUT7: INTEger := 16#800#;

constant IINPUT8: intEGER := 16#1000#;

constant IINPUt9: INTEger := 16#2000#;

constant IINPUT10: INTEGER := 16#3000#;

constant iinpuT11: INTeger := 16#8000#;

constant iiNPUT12: iNTEGER := 16#10000#;

constant IINPut13: INTEGER := 16#20000#;

constant iiNPUT14: iNTEGER := 16#40000#;

constant iinput15: INTEGER := 16#80000#;

constant Iinput16: INTEGEr := 16#100000#;

constant iinput17: INteger := 16#200000#;

constant iinput18: INTEGer := 16#300000#;

constant iinput19: Integer := 16#800000#;

constant iINPUT20: integer := 16#1000000#;

constant IINPUT21: integeR := 16#2000000#;

constant iINPUT22: INTEGER := 16#4000000#;

constant iinpuT23: INTEger := 16#8000000#;

constant iinput24: INTEGEr := 16#10000000#;

constant IINPUt25: integer := 16#20000000#;

constant IINPUT26: Integer := 16#40000000#;

constant iinput27: INTEGER := 16#40000000#;

constant ianyinput: inteGER := 16#7FFFFFF0#;

constant always: Integer := 16#01#;

constant zzero: inteGER := 16#08#;

constant NEGAtive: INTeger := 16#04#;

constant zero: INTEGER := 16#02#;

constant lte_zeRO: integer := 16#06#;

constant input0: INTeger := 16#010#;

constant input1: INTEGER := 16#020#;

constant input2: integer := 16#040#;

constant inpuT3: Integer := 16#080#;

constant input4: INTEGEr := 16#100#;

constant INPUT5: integer := 16#200#;

constant INPUt6: inteGER := 16#400#;

constant input7: INTEGER := 16#800#;

constant input8: INTEGER := 16#1000#;

constant INput9: integeR := 16#2000#;

constant INput10: integer := 16#3000#;

constant INput11: inTEGER := 16#8000#;

constant input12: INTEGER := 16#10000#;

constant input13: INTEGEr := 16#20000#;

constant input14: iNTEGER := 16#40000#;

constant INPUT15: INTEger := 16#80000#;

constant input16: inTEGER := 16#100000#;

constant input17: integer := 16#200000#;

constant INPUT18: INTEGEr := 16#300000#;

constant inPUT19: iNTEGER := 16#800000#;