coreabc.vhd

Actel Fusion System Management Development Kit UART Example. Contains Libero design using CoreABC. P

end if;
when "001" =>
if EN_AND = 1 then
ABCOIL0 <= accumulATOR and ABCoi10;
end if;
when "010" =>
if EN_OR = 1 then
ABCoIL0 <= ACCUMUlator or ABCoi10;
end if;
when "011" =>
if EN_XOR = 1 then
ABCoil0 <= accumulATOR xor ABCOI10;
end if;
when "100" =>
if EN_ADD = 1 or (EN_INC = 1 and (EN_MULT >= 1 or INSMODE > 0)) then
ABCOIL0 <= accUMULATOR+ABCOI10;
end if;
when "101" =>
if EN_SHL = 1 then
ABCOIl0 <= accuMULATOR(APB_DWIDTH-2 downto 0)&ABCi1i0;
end if;
when "110" =>
if EN_SHR = 1 then
ABCOIL0 <= ABCl1i0&ACCUMULator(APB_DWIDTH-1 downto 1);
end if;
when "111" =>
ABCOIL0 <= ABCoi10;
when others =>
ABCoIL0 <= ( others => '-');
end case;
end process;
process (ABCll00,instr_cmD,ABCoil0,PRDATA,IO_IN)
begin
if (EN_RAM > 0 and ABCLL00 = '1') or INSTr_cmd(1) = '0' then
ABCill0 <= ABCOIL0;
elsif EN_IOREAD = 1 and instr_cmd(0) = '1' then
ABCill0 <= ( others => '0');
ABCIll0(IIWIDTH-1 downto 0) <= IO_IN;
else
ABCill0 <= PRDATA(APB_DWIDTH-1 downto 0);
end if;
end process;
process (PCLK,RESETN)
begin
if RESETN = '0' then
accUMULATOR <= ( others => '0');
ABCLII0 <= '0';
ABCIII0 <= '0';
ABCO0I0 <= '0';
ABCL0I0 <= '0';
elsif PCLK'EVENT and PCLK = '1' then
if ABClli0 = '1' or ABCOII0 = '1' then
acCUMULATOr <= ABCILL0;
end if;
if isr = '0' and ABCili0 = '1' then
ABClii0 <= ABCll1(ABCilL0 = ABCLI10(APB_DWIDTH-1 downto 0));
ABCiii0 <= ABCill0(APB_DWIDTH-1);
end if;
if isr = '1' and ABCili0 = '1'
and EN_INT > 0 then
ABCO0I0 <= ABCLL1(ABCill0 = ABCli10(APB_DWIDTH-1 downto 0));
ABCL0I0 <= ABCill0(APB_DWIDTH-1);
end if;
if EN_INT = 0 then
ABCo0i0 <= '0';
ABCL0I0 <= '0';
end if;
end if;
end process;
ACCum_zero <= ABCo0i0 when isr = '1' else
ABClII0;
ACCum_neg <= ABCl0I0 when ISR = '1' else
ABCiII0;
ABColi0 <= '1' when (clEAN(zregisteR) = clean(ABCLi10(ZRWIDTH downto 0)) and ZRWIDTH > 0) else
'0';
process (instr_DATA,INSTR_scmd,IO_IN,ACCUM_Neg,ACCUm_zero,ABColi0)
variable ABClOO1: Std_logic_vECTOR(31 downto 0);
variable ABCiol: std_logic;
begin
ABCLOO1 := ( others => '0');
ABCLOO1(3 downto 0) := (ABCOLI0&ACcum_neg&ACCUM_ZEro&'1');
for ABCll in 0 to IFWIDTH-1
loop
ABCloo1(ABCll+4) := IO_IN(ABCLL);
end loop;
ABCiOL := '0';
for ABCLL in 0 to IFWIDTH+4-1
loop
ABCiol := ABCIOl or (INSTR_data(ABCll) and ABClOO1(ABCLL));
end loop;
FLAGS <= ABCIOL xnor inSTR_SCMD(0);
end process;
process (insTR_CMD,insTR_SCMD,ABClll0)
begin
ABCioi0 <= '-';
ABCloi0 <= '-';
case insTR_CMD is
when "010" =>
if Instr_scmd(0) = '1' then
ABCIOI0 <= '0';
ABCloi0 <= '-';
elsif EN_ACM = 1 and instr_scmD(1) = '1' then
ABCioi0 <= '1';
ABCloi0 <= '1';
else
ABCioi0 <= '1';
ABCLoi0 <= '0';
end if;
when "011" =>
if ABCLLL0 = '0' then
ABCioi0 <= '0';
ABCloi0 <= '-';
else
ABCioi0 <= '1';
ABCloi0 <= '0';
end if;
when others =>
ABCioi0 <= '-';
ABCLOI0 <= '-';
end case;
end process;
process (ABClOI0,Accumulator,acmdatA)
begin
ABClil0 <= accumulaTOR;
if EN_ACM = 1 and ABCLOi0 = '1' then
ABCLIL0(7 downto 0) <= acmdata;
end if;
end process;
process (ABCiOI0,instr_data,ABCLIl0)
begin
if ABCioi0 = '0' then
ABCiil0 <= instr_daTA;
else
ABCIIL0 <= ABCLIL0;
end if;
end process;
process (ABClil0,ABCiil0,ACCUmulator,INSTr_data)
begin
case EN_DATAM is
when 0 =>
ABCo0L0 <= ABClil0;
ABCL0L0 <= accumuLATOR;
ABCL1L0 <= accumuLATOR;
ABCi0l0 <= accUMULATOR;
when 1 =>
ABCo0l0 <= INSTR_DAta;
ABCL0L0 <= instr_data;
ABCL1L0 <= instr_data;
ABCI0L0 <= instr_dATA;
when 2 =>
ABCO0l0 <= ABCiil0;
ABCL0L0 <= ABCiil0;
ABCl1L0 <= ABCIIL0;
ABCi0l0 <= ABCiIL0;
when 3 =>
ABCo0l0 <= ABCLIL0;
ABCL0l0 <= accuMULATOR;
ABCl1l0 <= iNSTR_DATa;
ABCi0l0 <= iNSTR_DATa;
end case;
ABCo1l0 <= ( others => '0');
-- synthesis translate_off
ABCo1l0 <= ABCIIL0;
-- synthesis translate_on
end process;
process (ABCL1L0)
constant ABCoio0: integer := min(APB_DWIDTH,
ZRWIDTH);
constant M: INTEger := max(1,
ZRWIDTH-1);
begin
ABCI1L0 <= ( others => ABCl1l0(APB_DWIDTH-1));
for ABCll in 0 to ABCoio0-1
loop
ABCI1l0(ABCLl) <= ABCl1l0(ABCll);
end loop;
end process;
ABCLL00 <= ABCll1(CLEAN(iNSTR_CMD) = "011" and EN_RAM > 0
and clean(iNSTR_SCMd(2 downto 1)) /= "11");
process (STKPTr)
variable ABCiOO1: std_loGIC_VECtor(STWIDTH-1 downto 0);
begin
ABCIoo1 := clean(stkptr(STWIDTH-1 downto 0));
ABCOLi <= ( others => '1');
ABClli <= ( others => '1');
ABColi(STWIDTH-1 downto 0) <= ABCioo1-1;
ABClli(STWIDTH-1 downto 0) <= ABCIoo1+1;
end process;
ABCoLL0 <= ABCLLI;
ABCo000 <= ABCLL1((INTREQ = '1' and (EN_INT = 1)) or (INTREQ = '0' and (EN_INT = 2)));
ABCiO00 <= PREADY;
ABCi000 <= ABCLL1(INSMODE <= 1) or not ABCl11;
process (PCLK,RESETN)
begin
if RESETN = '0' then
ABClo00 <= '0';
ABCoo00 <= '0';
ABCIli0 <= '0';
ABClli0 <= '0';
ABCio10 <= ABCLO10;
ABCi0i0 <= '0';
ABCO1I0 <= '0';
ABCol00 <= '0';
SMADDR <= ( others => '1');
ZREGISter <= ( others => '0');
IO_OUT <= ( others => '0');
Stkptr <= ( others => '1');
Isr <= '0';
ABCL000 <= '0';
elsif PCLK'event and PCLK = '1' then
ABCLO00 <= '0';
ABCOO00 <= '0';
ABCILI0 <= '0';
ABClli0 <= '0';
ABCOL00 <= '0';
ABCl000 <= '0';
case ABCio10 is
when ABCL100 =>
if iNITDONE = '1' or INSMODE = 0
or INSMODE = 2 then
if EN_INT > 0 and ABCo000 = '1'
and ISR = '0' then
ISR <= '1';
Stkptr <= ABCOli;
ABCO1I0 <= '1';
ABCIO10 <= ABCI100;
ABCol00 <= '1';
else
ABCio10 <= ABCI100;
end if;
end if;
when ABCi100 =>
if ABCI000 = '1' then
if ABCO1i0 = '1' then
ABCio10 <= ABClo10;
else
case instr_cMD is
when "000" =>
ABCIO10 <= ABCLO10;
ABCILI0 <= '1';
ABCLLI0 <= '1';
when "001" =>
ABCIo10 <= ABClo10;
ABCILI0 <= '1';
when "010" =>
if EN_ACM = 1 and instr_SCMD(1 downto 0) = "10" then
ABClo00 <= acmdo;
else
ABClo00 <= '1';
end if;
ABCio10 <= ABCoo10;
when "011" =>
case INSTr_scmd is
when "000" =>
if ZRWIDTH > 0 then
zregister(ZRWIDTH-1 downto 0) <= ABCi1l0(ZRWIDTH-1 downto 0);
end if;
when "001" =>
if ZRWIDTH > 0 then
ZREGISTer(ZRWIDTH-1 downto 0) <= zREGISTER(ZRWIDTH-1 downto 0)+ABCi1l0(ZRWIDTH-1 downto 0);
end if;
when "010" =>
if EN_RAM > 0 then
ABCol00 <= '1';
end if;
when "011" =>
if EN_RAM > 0 then
ABCILi0 <= '1';
ABClli0 <= '1';
end if;
when "100" =>
if EN_PUSH = 1 then
STKPTR <= ABColi;
ABCOL00 <= '1';
end if;
when "101" =>
if EN_PUSH = 1 then
STKPTR <= ABCLLI;
ABCilI0 <= '1';
ABClli0 <= '1';
end if;
when "110" =>
if EN_IOREAD = 1 then
ABCILI0 <= '1';
ABClli0 <= '1';
end if;
when "111" =>
if EN_IOWRT = 1 then
IO_OUT(IOWIDTH-1 downto 0) <= ABCI0l0(IOWIDTH-1 downto 0);
end if;
when others =>
end case;
ABCio10 <= ABClo10;
when "100" =>
if flags = '1' then
ABCi0i0 <= '1';
end if;
ABCio10 <= ABCLO10;
when "101" =>
if EN_CALL = 1 and FLAGS = '1' then
STKPTR <= ABColi;
ABCOL00 <= '1';
ABCI0I0 <= '1';
end if;
ABCIO10 <= ABClO10;
when "110" =>
if (EN_CALL = 1 or EN_INT > 0) and fLAGS = '1' then
ABCio10 <= ABCLO10;
stkptr <= ABClli;
ABCi0i0 <= '1';
if INSTR_SCmd(1) = '1' and EN_INT > 0 then
Isr <= '0';
end if;
else
ABCIO10 <= ABCLO10;
end if;
when "111" =>
ABCIO10 <= ABCLO10;
when others =>
ABCio10 <= ABCLO10;
end case;
end if;
end if;
when ABCoo10 =>
ABCOO00 <= '1';
ABCLO00 <= '1';
if (PREADY = '1' and ABCoo00 = '1') or ABClo00 = '0' then
ABClo00 <= '0';
ABCOo00 <= '0';
ABCIO10 <= ABClO10;
end if;
when ABClo10 =>
if ABCI000 = '1' then
ABCL000 <= '1';
ABCo1i0 <= '0';
ABCI0i0 <= '0';
if ABCo1I0 = '1' and EN_INT > 0 then
sMADDR <= cONV_STD_logic_veCTOR(ISRADDR,
ICWIDTH);
elsif ABCi0i0 = '1' then
SMADDr <= INSTR_Addr(ICWIDTH-1 downto 0);
if (EN_CALL = 1 or EN_INT > 0) and INSTR_CMd(1) = '1' then
smaddr <= ABCli00(ICWIDTH-1 downto 0);
end if;
if (INSTR_Cmd(1) = '0' and instr_scmD(1) = '1') then
SMADdr <= smadDR;
end if;
if instr_cmd = "100" and instr_sCMD(1) = '1' then
ABCl000 <= '0';
end if;
else
smaddr <= SMADDR+1;
end if;
ABCio10 <= ABCL100;
end if;
end case;
if EN_CALL = 0 and EN_INT = 0 then
stkPTR <= ( others => '1');
end if;
if STWIDTH < 8 then
stkPTR(7 downto STWIDTH) <= ( others => '1');
end if;
if ZRWIDTH = 0 then
zregISTER <= ( others => '0');
end if;
if EN_RAM = 0 and EN_INT = 0
and EN_CALL = 0
and EN_PUSH = 0 then
ABCol00 <= '0';
end if;
if EN_INT = 0 then
isr <= '0';
ABCo1i0 <= '0';
end if;
if EN_IOWRT = 0 then
IO_OUT <= ( others => '0');
end if;
zregiSTER(ZRWIDTH) <= '0';
if INSMODE /= 2 then
ABCl000 <= '0';
end if;
end if;
end process;
INTACT <= isr;
process (INSTR_addr,Instr_scmd,zregISTER)
constant ABCoio0: iNTEGER := MIN(ZRWIDTH,
APB_AWIDTH);
begin
PADDR <= ( others => '0');
if EN_INDIRECT = 1 and instr_SCMD(2) = '1'
and ZRWIDTH > 0 then
PADDR(ABCOIo0-1 downto 0) <= zreGISTER(ABCoio0-1 downto 0);
else
PADDR(APB_AWIDTH-1 downto 0) <= instr_addr;
end if;
end process;
process (ABCo0l0)
begin
PWDATA <= ( others => '0');
PWDATA(APB_DWIDTH-1 downto 0) <= ABCO0L0;
end process;
PENABLE <= ABCOO00;
PWRITE <= not (Instr_scmd(0) and Instr_scmd(1));
ABCoiI0 <= ABCoo00 and instr_sCMD(0)
and instR_SCMD(1);
process (ABClo00,INstr_slot)
variable ABColo1: STD_logic_veCTOR(APB_SWIDTH downto 0);
begin
PSEL <= ( others => '0');
ABColO1 := INSTR_SLot;
-- synthesis translate_off
ABCOLO1 := ( others => '0');
for ABCll in ABCOLO1'range
loop
if INSTR_SLot(ABCll) = '1' then
ABColO1(ABCLL) := '1';
end if;
end loop;
-- synthesis translate_on
if APB_SDEPTH = 1 then
PSEL(0) <= ABCLO00;
else
for ABCll in 0 to APB_SDEPTH-1
loop
PSEL(ABCLL) <= ABClo00 and ABCll1(conv_INTEGER(ABColo1) = ABCLL);
end loop;
end if;
end process;
-- synthesis translate_off
Debug1 <= ABCll1(ABCi000 = '1' and ABCio10 = ABCi100);
debug2 <= ABCll1(ABCIO10 = ABCoo10 and PREADY = '1'
and ABCoo00 = '1'
and instr_scmD(1 downto 0) = "11");
ABCllo1: DEBUGBLK
generic map (DEBUG => DEBUG,
AWIDTH => APB_AWIDTH,
DWidth => APB_DWIDTH,
SWIdth => APB_SWIDTH,
SDEPTh => APB_SDEPTH,
ICWIDTH => ICWIDTH,
Icdepth => ABCOI0,
zrwidth => ZRWIDTH,
Iiwidth => IIWIDTH,
IOWidth => IOWIDTH,
IRWIdth => ABCiol0,
eN_MULT => EN_MULT)
port map (PCLK => PCLK,
RESEtn => RESETN,
SMADdr => SMADDR,
ISR => isr,
instr_cMD => INSTR_CMd,
instr_SCMD => INSTr_scmd,
inSTR_DATa => instr_data,
iNSTR_ADdr => instr_addr,
inSTR_SLOt => INStr_slot,
prdata => PRDATA(APB_DWIDTH-1 downto 0),
PWDATA => ABCo1l0,
Accum_old => AccumulatoR,
accUM_NEW => ABCILL0,
ACCUM_zero => accum_zero,
accuM_NEG => accum_NEG,
flags => flaGS,
RAmdout => RAMDOUT,
stkptR => stKPTR,
ZREGister => zregisTER,
acmdo => acmdo,
deBUG1 => DEbug1,
debug2 => debug2);
-- synthesis translate_on
end RTl;