coreabc.vhd

Actel Fusion System Management Development Kit UART Example. Contains Libero design using CoreABC. P

-- Copyright 2007 Actel Corporation.  All rights reserved.
-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN 
-- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED 
-- IN ADVANCE IN WRITING.  
-- Rev: 2.3   01Mar07 IPB  : Production Release   
library Ieee;
use IEEe.STD_logIC_1164.all;
use IEEE.sTD_LOGIC_arith.all;
use IEEE.STd_logic_unSIGNED.all;
library CoreABC_LIB;
use CoREABC_LIB.Support.all;
entity COreABC is
generic (ID: integeR range 0 to 9;
family: integer range 0 to 21;
apB_AWIDTH: integer range 8 to 16;
Apb_dwidth: integer range 8 to 32;
apb_sDEPTH: INTEGER range 1 to 16;
icwiDTH: integER range 1 to 16;
zrwidth: INTEGEr range 0 to 16;
ifWIDTH: integeR range 0 to 28;
iiwIDTH: integer range 1 to 32;
IOWIDth: integER range 1 to 32;
STWIDTh: integeR range 1 to 8;
en_ram: INTEGEr range 0 to 1;
en_and: iNTEGER range 0 to 1;
EN_XOr: intEGER range 0 to 1;
en_or: inteGER range 0 to 1;
en_ADD: iNTEGER range 0 to 1;
en_iNC: INteger range 0 to 1;
EN_shl: INteger range 0 to 1;
EN_shr: Integer range 0 to 1;
EN_CAll: Integer range 0 to 1;
EN_PUsh: Integer range 0 to 1;
EN_MUlt: INteger range 0 to 3;
en_ACM: iNTEGER range 0 to 1;
EN_DAtam: integer range 0 to 3;
en_INT: INTEGER range 0 to 2;
en_IOREAD: iNTEGER range 0 to 1;
EN_iowrt: INteger range 0 to 1;
en_aluRAM: integer range 0 to 1;
en_INDIRECt: INTeger range 0 to 1;
ISRADDR: integER range 0 to 65536;
DEBug: integeR range 0 to 1;
INSmode: INTEGER range 0 to 2;
initWIDTH: integer range 1 to 16;
tESTMODE: inteGER range 0 to 99 := 0); port (pCLK: in std_lOGIC;
NSYSreset: in STD_LOGic;
pRESETN: out Std_logic;
PENABLE: out std_loGIC;
PWRite: out std_LOGIC;
PSEL: out stD_LOGIC_vector(APB_SDEPTH-1 downto 0);
PADDR: out std_lOGIC_VEctor(APB_AWIDTH-1 downto 0);
PWDATA: out STD_logic_veCTOR(APB_DWIDTH-1 downto 0);
PRDATA: in std_logIC_VECTor(APB_DWIDTH-1 downto 0);
PREady: in STD_LOgic;
IO_IN: in Std_logic_vECTOR(IIWIDTH-1 downto 0);
IO_OUT: out std_loGIC_VECtor(IOWIDTH-1 downto 0);
INtreq: in sTD_LOGIC;
intACT: out std_loGIC;
INITDATVal: in std_logic;
INItdone: in STD_logic;
INITADDR: in std_LOGIC_vector(INITWIDTH-1 downto 0);
INITDATA: in std_LOGIC_vector(8 downto 0));
end CoreABC;

architecture RTL of COREABC is

constant iwwidth: inTEGER := 32+16+4+6;

constant ABCiol0: INTEGER := ABCOLO0(EN_RAM,
EN_CALL,
APB_DWIDTH,
ICWIDTH);

constant ABCoi0: inteGER range 1 to 65536 := 2**ICWIDTH;

constant APB_SWIDTH: INteger range 0 to 4 := calc_swiDTH(APB_SDEPTH);

constant ABCO00: integer := APB_AWIDTH+APB_DWIDTH+APB_SWIDTH+6;

signal Smaddr: STD_Logic_vectOR(ICWIDTH-1 downto 0);

signal instructiON: stD_LOGIC_vector(iwwidTH-1 downto 0);

signal stkptr: Std_logic_vECTOR(7 downto 0);

signal ABColi: STD_logic_vecTOR(7 downto 0);

signal ABClLI: STD_logic_vecTOR(7 downto 0);

signal ABCOLL0: std_logic_VECTOR(7 downto 0);

signal instr_CMD: Std_logic_vECTOR(2 downto 0);

signal instr_scmd: STD_LOgic_vectoR(2 downto 0);

signal INSTR_slot: std_loGIC_VECtor(APB_SWIDTH downto 0);

signal instr_aDDR: Std_logic_vECTOR(APB_AWIDTH-1 downto 0);

signal inSTR_DATA: std_logic_VECTOR(APB_DWIDTH-1 downto 0);

signal ABCLLl0: sTD_LOGIC;

signal accumulaTOR: std_logiC_VECTOr(APB_DWIDTH-1 downto 0);

signal ABCILL0: std_loGIC_VECtor(APB_DWIDTH-1 downto 0);

signal ABCOIL0: STD_LOGic_vector(APB_DWIDTH-1 downto 0);

signal ABCLIL0: std_LOGIC_vector(APB_DWIDTH-1 downto 0);

signal ABCiil0: stD_LOGIC_vector(APB_DWIDTH-1 downto 0);

signal ABCo0L0: stD_LOGIC_vector(APB_DWIDTH-1 downto 0);

signal ABCL0L0: STD_logic_vecTOR(APB_DWIDTH-1 downto 0);

signal ABCi0l0: STD_logic_veCTOR(APB_DWIDTH-1 downto 0);

signal ABCo1l0: stD_LOGIC_vector(APB_DWIDTH-1 downto 0);

signal ABCl1L0: std_LOGIC_vector(APB_DWIDTH-1 downto 0);

signal ABCi1l0: stD_LOGIC_vector(ZRWIDTH-1 downto 0);

signal ABCOOI0: STD_LOGIc_vector(APB_DWIDTH-1 downto 0);

signal ABCloi0: STD_Logic;

signal ABCioi0: STD_LOgic;

signal zreGISTER: std_lOGIC_VEctor(ZRWIDTH downto 0);

signal ABCOLI0: stD_LOGIC;

signal ABClli0: STD_LOGic;

signal ABCili0: sTD_LOGIC;

signal ABCOII0: std_logic;

signal ACCUM_ZEro: std_logic;

signal ACCUM_NEg: STD_LOGic;

signal ABClii0: std_loGIC;

signal ABCiii0: STD_LOgic;

signal ABCo0I0: STD_LOGIc;

signal ABCL0i0: Std_logic;

signal FLags: STD_Logic;

signal ABCi0i0: std_logiC;

signal ABCO1I0: STD_Logic;

signal ABCl1i0: STD_logic;

signal ABCi1i0: STd_logic;

signal ABCOO00: STD_LOgic;

signal ABClo00: std_logic;

signal ABCio00: Std_logic;

signal ABCol00: STD_logic;

signal ABCll00: STD_LOgic;

signal ABCIL00: std_logiC_VECTOr(7 downto 0);

signal ABCoi00: STD_Logic_vectoR(7 downto 0);

signal ABCLI00: std_LOGIC_vector(ABCiol0-1 downto 0);

signal ABCII00: std_logic_VECTOR(ABCiOL0-1 downto 0);

signal RAMdout: Std_logic_vECTOR(APB_DWIDTH-1 downto 0);

signal isr: std_loGIC;

signal ABCo000: STD_LOGIc;

signal ACMdo: STD_logic;

signal Acmdata: sTD_LOGIC_vector(7 downto 0);

signal debug1: std_logIC;

signal DEBug2: STD_LOgic;

signal ABCl000: STD_LOgic;

signal ABCl11: STD_LOGic;

signal ABCi000: std_logIC;

type ABCo100 is (ABCL100,ABCI100,ABCoo10,ABCLO10);

signal ABCio10: ABCo100;

signal ABCOL10: STD_LOGic;

signal ABCll10: Std_logic;

signal RESETN: std_LOGIC;

signal ABCil10: Std_logic;

signal ABCoi10: STD_LOgic_vectoR(APB_DWIDTH-1 downto 0);

signal ABCli10: STD_logic_vecTOR(31 downto 0);

signal ABCIO1: Std_logic;

signal ABCOL1: STD_logic;

begin
ABCLI10 <= ( others => '0');
ABCio1 <= '0';
ABCol1 <= '1';
process (PCLK,NSYSRESet)
begin
if nsysRESET = '0' then
ABCOL10 <= '0';
ABCll10 <= '0';
elsif PCLK'EVEnt and PCLK = '1' then
ABCOl10 <= '1';
ABCll10 <= ABCOL10;
end if;
end process;
PRESETN <= ABCLL10;
RESETN <= ABCLl10;
ABCLI1:
if EN_RAM > 0 or EN_CALL > 0
or EN_INT > 0
or EN_PUSH > 0
generate
process (instr_addr,instR_CMD,instr_scmd,ABCLLl0,ABCl0l0,ABColl0,SMaddr,ABCO1I0,ABCio10)
begin
ABCil00 <= ( others => '-');
ABCii00 <= ( others => '-');
if (INSTR_cmd = "011" or ABClll0 = '1') and EN_RAM > 0
and ABCo1I0 = '0' then
ABCii00(APB_DWIDTH-1 downto 0) <= ABCl0l0;
ABCil00 <= iNSTR_ADDr(7 downto 0);
if Instr_cmd = "011" and INSTR_scmd(2) = '1'
and EN_PUSH = 1 then
ABCIL00 <= ABColL0;
end if;
elsif EN_CALL > 0 or EN_INT > 0 then
ABCIL00 <= ABCOLL0;
if EN_INT = 1 and ABCO1I0 = '1' then
ABCii00(ICWIDTH-1 downto 0) <= smadDR;
else
ABCii00(ICWIDTH-1 downto 0) <= Smaddr+1;
end if;
end if;
end process;
process (ABCil00)
begin
ABCoi00 <= ( others => '0');
for ABCLL in ABCil00'range
loop
if ABCIL00(ABCLl) = '1' then
ABCoi00(ABCll) <= '1';
end if;
end loop;
end process;
ABCoi1: ABCLI0i
generic map (DWIDTH => ABCIOL0,
FAMILY => FAMILY)
port map (clk => PCLK,
RESETN => RESETN,
WEN => ABCol00,
ADDR => ABCOI00,
wd => ABCii00,
RD => ABCLi00);
RAMDOut <= ABCli00(APB_DWIDTH-1 downto 0);
end generate;
ABCii10:
if EN_RAM = 0 and EN_CALL = 0
and EN_INT = 0
and EN_PUSH = 0
generate
ABCIL00 <= ( others => '0');
ABCIi00 <= ( others => '0');
ramdout <= ( others => '0');
ABCOI00 <= ( others => '0');
ABClI00 <= ( others => '0');
end generate;
ABCO010:
if EN_ACM = 1
generate
ABCl010: ACMTABLE
generic map (id => ID,
tm => TESTMODE)
port map (ACMAddr => accumulaTOR(7 downto 0),
acmdATA => ACMDATa,
acmdo => Acmdo);
end generate;
ABCi010:
if EN_ACM = 0
generate
acMDATA <= ( others => '0');
ACMDO <= '0';
end generate;
urom:
if INSMODE = 0 or (INSMODE = 2 and FAMILY /= 17)
generate
UROM: INSTRUCTions
generic map (testmoDE => TESTMODE,
ID => ID,
en_mult => EN_MULT,
eN_INC => EN_INC,
AWIDTH => APB_AWIDTH,
dwIDTH => APB_DWIDTH,
SWIDTH => APB_SWIDTH,
icwIDTH => ICWIDTH,
iIWIDTH => IIWIDTH,
ifwidTH => IFWIDTH,
iwwidth => IWwidth)
port map (ADDRess => SMADdr,
INSTRUction => instructiON);
process (PCLK)
begin
if PCLK'eveNT and PCLK = '1' then
iNSTR_CMD <= INSTRuction(2 downto 0);
instr_SCMD <= INSTruction(5 downto 3);
INStr_slot <= instRUCTION(APB_SWIDTH+6 downto 6);
INSTR_slot(APB_SWIDTH) <= '0';
Instr_addr <= instRUCTION(APB_AWIDTH-1+4+6 downto 4+6);
instr_DATA <= INSTruction(APB_DWIDTH-1+16+4+6 downto 16+4+6);
ABClll0 <= INSTruction(6);
end if;
end process;
ABCl11 <= '0';
end generate;
ABCo110:
if INSMODE = 1
generate
ABCo110: ABCIL0
generic map (TESTMODE => TESTMODE,
AWidth => APB_AWIDTH,
dwidth => APB_DWIDTH,
SWIDth => APB_SWIDTH,
ICWIDTH => ICWIDTH,
ABCoi0 => ABCoi0,
IWWIDTh => iwwidth,
INITWIDTH => INITWIDTH,
ID => id)
port map (clk => PCLK,
ABClI0 => RESETN,
initdatVAL => inITDATVAL,
INitdone => iniTDONE,
INITADDR => INITADDR,
INITDATA => INITDATA,
addRESS => smaDDR,
instructION => Instruction);
process (INSTruction)
begin
INSTR_Cmd <= inSTRUCTIOn(2 downto 0);
iNSTR_SCMd <= InstructioN(5 downto 3);
INSTr_slot <= instrUCTION(APB_SWIDTH+6 downto 6);
instr_sLOT(APB_SWIDTH) <= '0';
INstr_addr <= insTRUCTION(APB_AWIDTH-1+4+6 downto 4+6);
INSTR_data <= INstruction(APB_DWIDTH-1+16+4+6 downto 16+4+6);
ABClll0 <= INStruction(6);
end process;
ABCl11 <= '0';
end generate;
ABCl110:
if INSMODE = 2 and FAMILY = 17
generate
urom: ABCi01
generic map (AWIdth => APB_AWIDTH,
dwidth => APB_DWIDTH,
swidTH => APB_SWIDTH,
ICWIDTH => ICWIDTH,
ABCOI0 => ABCoi0,
iwwiDTH => iWWIDTH,
ID => id)
port map (clk => PCLK,
ABCLI0 => RESETN,
ABCo11 => ABCL000,
ABCl11 => ABCl11,
ADDRESS => SMADDR,
instRUCTION => instructiON);
process (insTRUCTION)
begin
instr_CMD <= INStruction(2 downto 0);
INSTR_Scmd <= INStruction(5 downto 3);
instr_SLOT <= INSTRUCtion(APB_SWIDTH+6 downto 6);
INSTR_Slot(APB_SWIDTH) <= '0';
INSTR_addr <= insTRUCTION(APB_AWIDTH-1+4+6 downto 4+6);
INSTR_data <= instructioN(APB_DWIDTH-1+16+4+6 downto 16+4+6);
ABClll0 <= INSTRUction(6);
end process;
end generate;
process (INSTR_Data,accumulatOR)
begin
ABCL1i0 <= '-';
ABCI1I0 <= '-';
if EN_SHL = 1 or EN_SHR = 1 then
case inSTR_DATa(1 downto 0) is
when "00" =>
ABCl1I0 <= '0';
ABCi1i0 <= '0';
when "01" =>
ABCl1i0 <= '1';
ABCI1i0 <= '1';
when "10" =>
ABCl1i0 <= accumuLATOR(APB_DWIDTH-1);
ABCI1i0 <= accumulaTOR(0);
when "11" =>
ABCl1I0 <= ACCUmulator(0);
ABCi1i0 <= aCCUMULATOr(APB_DWIDTH-1);
when others =>
end case;
end if;
end process;
ABCil10 <= ABCLl1(EN_RAM = 1) and (ABCll00 or (ABCLL1(EN_ALURAM = 1) and ABClll0));
process (inSTR_DATA,ABCIL10,RAmdout)
variable ABCIOO0: stD_LOGIC_vector(APB_DWIDTH-1 downto 0);
begin
if ABCil10 = '0' then
ABCoi10 <= clean(instr_data);
else
ABCoi10 <= CLEAN(ramdouT);
end if;
end process;
process (accumuLATOR,ABCOI10)
variable ABCI110: std_lOGIC_VEctor(2*APB_DWIDTH-1 downto 0);
variable a,b: STD_Logic_vectOR(APB_DWIDTH/2-1 downto 0);
begin
case EN_MULT is
when 1 =>
a := acCUMULATOr(APB_DWIDTH/2-1 downto 0);
b := ABCoi10(APB_DWIDTH/2-1 downto 0);
ABCoOI0 <= a*b;
when 2 =>
ABCi110 := acCUMULATOr*ABCoi10;
ABCoOI0 <= ABCi110(APB_DWIDTH-1 downto 0);
when 3 =>
ABCi110 := ACCUMULATor*ABCoi10;
ABCOoi0 <= ABCi110(2*APB_DWIDTH-1 downto APB_DWIDTH);
when others =>
ABCooi0 <= ( others => '-');
end case;
end process;
process (ABCll00,INSTR_scmd,accuMULATOR,instr_daTA,ABCL1I0,ABCi1i0,ABCoi10,ABCOoi0)
variable ABCOOO1: std_LOGIC_Vector(2 downto 0);
begin
ABCoil0 <= ( others => '-');
ABCOOo1 := inSTR_SCMD;
if ABCLL00 = '1' then
ABCOOO1 := "111";
end if;
case ABCOOO1 is
when "000" =>
if EN_INC = 1 and EN_MULT = 0
and (INSMODE = 0 or (INSMODE = 2 and FAMILY /= 17)) then
ABCoil0 <= accumulaTOR+1;
end if;
if EN_MULT >= 1 then
ABCoil0 <= ABCooi0;