coreabc.cxf

Actel Fusion System Management Development Kit UART Example. Contains Libero design using CoreABC. P

<?xml version="1.0" encoding="UTF-8"?>
<component>
<vendor>Actel</vendor>
<library>DirectCore</library>
<name>COREABC</name>
<version>2.3.165</version>
<views>
<view>
<name>HDL</name>
<fileSetRef>HDL_FILESET</fileSetRef>
</view>
<view>
<name>Simulation</name>
<fileSetRef>STIMULUS_FILESET</fileSetRef>
<fileSetRef>ANY_SIMULATION_FILESET</fileSetRef>
<fileSetRef></fileSetRef>
</view>
</views>
<fileSets>
<fileSet fileSetId="ANY_SIMULATION_FILESET">
<file>
<name>mti/scripts/wave_abc_user.do</name>
<userFileType>DO</userFileType>
<vendorExtension>
<IncludeInRunDo/>
</vendorExtension>
</file>
<file>
<name>mti/scripts/runall.do</name>
<userFileType>DO</userFileType>
</file>
<file>
<name>mti/scripts/makehex.do</name>
<userFileType>DO</userFileType>
</file>
</fileSet>
<fileSet fileSetId="HDL_FILESET">
<file>
<name>rtl/vhdl/core_obfuscated/support.vhd</name>
<fileType>vhdlSource</fileType>
<logicalName>COREABC_LIB</logicalName>
</file>
<file>
<name>rtl/vhdl/core_obfuscated/ramblocks.vhd</name>
<fileType>vhdlSource</fileType>
<logicalName>COREABC_LIB</logicalName>
</file>
<file>
<name>rtl/vhdl/core_obfuscated/acmtable.vhd</name>
<fileType>vhdlSource</fileType>
<logicalName>COREABC_LIB</logicalName>
</file>
<file>
<name>rtl/vhdl/core_obfuscated/instructram.vhd</name>
<fileType>vhdlSource</fileType>
<logicalName>COREABC_LIB</logicalName>
</file>
<file>
<name>rtl/vhdl/core_obfuscated/instructions.vhd</name>
<fileType>vhdlSource</fileType>
<logicalName>COREABC_LIB</logicalName>
</file>
<file>
<name>rtl/vhdl/core_obfuscated/debugblk.vhd</name>
<fileType>vhdlSource</fileType>
<logicalName>COREABC_LIB</logicalName>
</file>
<file>
<name>rtl/vhdl/core_obfuscated/CoreABC.vhd</name>
<fileType>vhdlSource</fileType>
<logicalName>COREABC_LIB</logicalName>
</file>
<file>
<name>rtl/vhdl/core_obfuscated/components.vhd</name>
<fileType>vhdlSource</fileType>
<logicalName>COREABC_LIB</logicalName>
</file>
<file>
<name>rtl/vhdl/core_obfuscated/iram512x9_fusion.vhd</name>
<fileType>vhdlSource</fileType>
<logicalName>COREABC_LIB</logicalName>
</file>
<file>
<name>rtl/vhdl/core_obfuscated/ram256x16_fusion.vhd</name>
<fileType>vhdlSource</fileType>
<logicalName>COREABC_LIB</logicalName>
</file>
<file>
<name>rtl/vhdl/core_obfuscated/instructnvm.vhd</name>
<fileType>vhdlSource</fileType>
<logicalName>COREABC_LIB</logicalName>
</file>
</fileSet>
<fileSet fileSetId="STIMULUS_FILESET">
<file>
<name>coreparameters.vhd</name>
<fileType>vhdlSource</fileType>
<logicalName>COREABC_LIB</logicalName>
</file>
<file>
<name>rtl/vhdl/test/testsupport.vhd</name>
<fileType>vhdlSource</fileType>
<logicalName>COREABC_LIB</logicalName>
</file>
<file>
<name>rtl/vhdl/test/apbmodel.vhd</name>
<fileType>vhdlSource</fileType>
<logicalName>COREABC_LIB</logicalName>
</file>
<file>
<name>rtl/vhdl/test/makehex.vhd</name>
<fileType>vhdlSource</fileType>
<logicalName>COREABC_LIB</logicalName>
</file>
<file>
<name>rtl/vhdl/test/createhex.vhd</name>
<fileType>vhdlSource</fileType>
<logicalName>COREABC_LIB</logicalName>
</file>
<file>
<name>rtl/vhdl/test/initgen.vhd</name>
<fileType>vhdlSource</fileType>
<logicalName>COREABC_LIB</logicalName>
</file>
<file>
<name>rtl/vhdl/test/testbench.vhd</name>
<fileType>vhdlSource</fileType>
<logicalName>COREABC_LIB</logicalName>
<vendorExtension>
<ModuleUnderTest>testbench</ModuleUnderTest>
<SimulationTime>-all</SimulationTime>
</vendorExtension>
</file>
</fileSet>
</fileSets>
<vendorExtension>
<libraries><library>
<name>COREABC_LIB</name>
<path>mti/lib_vhdl_obs/COREABC_LIB</path>
</library>
</libraries>
<type>CC_INTERNAL</type>
<fileSetRulesParameters>
<fileSetRuleParameter name="FAMILY">17</fileSetRuleParameter>
<fileSetRuleParameter name="TESTBENCH">User</fileSetRuleParameter>
<fileSetRuleParameter name="HDL_license">O</fileSetRuleParameter>
</fileSetRulesParameters>
</vendorExtension>
</component>