tbpack.vhd

Actel Fusion System Management Development Kit UART Example. Contains Libero design using CoreABC. P

-- *********************************************************************/ 
-- Copyright 1998 Actel Corporation.  All rights reserved.
--  
-- File:  TBPACK.VHD
--
-- Description: Package used by the Testbench for the UART
--
-- Rev: 1.0 08Apr98 IPB  Development 1.0   
--
-- Notes:
--
-- *********************************************************************/ 


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;

library std;
use std.textio.all;

use work.textio.all;


package tbpack is
    
    ------------------------------------------------------------------
    -- Usefull Types 
    --       
    
    subtype byte is std_logic_vector(7 downto 0); 
    type INTEGER_ARRAY is array ( INTEGER range <>) of INTEGER;
    
    ------------------------------------------------------------------
    -- Record Structures used by the testbench 
    --       
    
    type oddeven is ( ODD,EVEN);
    
    type PASSCHECK is
    record
        n : integer;
        result  : integer_array ( 0 to 255) ;
    end record;  

    type TUARTconfig is
    record
        bit8       : std_logic;
        parity_en  : std_logic;
        odd_n_even : std_logic;
    end record;  
    
    type TUARTstatus is
    record
        parity_err    : std_logic;
        overflow      : std_logic;
        txrdy         : std_logic;
        rxrdy  : std_logic;
        UART_data_out : std_logic_vector(7 downto 0);
    end record;
    
    type Tcpucontrol is
    record
        sel1  : std_logic; 
        sel2  : std_logic; 
        WEn   : std_logic; 
        OEn   : std_logic; 
        data  : std_logic_vector(7 downto 0);
    end record;
    
    
    ------------------------------------------------------------------
    -- package declarations
    --       
    

    procedure printpass(
        passc  : in  passcheck
        );
    
    procedure printnewtest( str : STRING);
            
    procedure printerror(
        ERR  : inout BOOLEAN;
        str  : STRING);
        
    procedure waitclocks( N   : in INTEGER;
        signal clk : in std_logic);
    
    
    procedure cpu_write(
        N       : in  INTEGER range 1 to 2;
        data    : in  std_logic_vector;
        signal  clk     : in  std_logic;
        signal  control : out Tcpucontrol ); 
    
    procedure cpu_read( 
        N       : in  INTEGER range 1 to 2;
        data    : out std_logic_vector;
        signal  clk     : in  std_logic;
        signal  control : out Tcpucontrol;
        signal  status  : in  TUARTstatus ); 

    procedure txrxtest( 
        count              : in    INTEGER range 1 to 256;
        signal clk         : in    std_logic;
        signal cpucontrol  : out   Tcpucontrol;
        signal UARTstatus1 : in    TUARTstatus;
        signal UARTstatus2 : in    TUARTstatus;
        err               : inout BOOLEAN; 
        signal passc               : inout passcheck ); 

     procedure paritytest( 
        count              : in    INTEGER range 1 to 256;
        RX_FIFO            : in    INTEGER;
        signal clk         : in    std_logic;
        signal cpucontrol  : out   Tcpucontrol;
        signal UARTstatus1 : in    TUARTstatus;
        signal UARTstatus2 : in    TUARTstatus;
        signal UARTconfig1 : out   TUARTconfig;
        signal UARTconfig2 : out   TUARTconfig;
        constant config1     : in    std_logic_vector(2 downto 0);
        constant config2     : in    std_logic_vector(2 downto 0);
        err                : inout BOOLEAN ;
        signal passc               : inout passcheck ); 

     procedure testoverflow(
        signal clk          : in      std_logic;
        signal cpucontrol   : out     Tcpucontrol;
        signal UARTstatus1  : in      TUARTstatus;
        signal UARTstatus2  : in      TUARTstatus;
        err                 : inout   BOOLEAN ;
        signal passc               : inout passcheck ); 
    
    procedure testoverflowfifo( 
        count              : in    INTEGER range 1 to 256;
        signal clk         : in    std_logic;
        signal cpucontrol  : out   Tcpucontrol;
        signal UARTstatus1 : in    TUARTstatus;
        signal UARTstatus2 : in    TUARTstatus;
        err               : inout BOOLEAN; 
        signal passc               : inout passcheck ); 
    
    
end tbpack;

------------------------------------------------------------------
------------------------------------------------------------------
------------------------------------------------------------------


package body tbpack is
    
    
    ------------------------------------------------------------------
    -- Misc Print Routines
    --       
    
--    procedure printf( str  : STRING) is
--    file FSTR : TEXT is out"STD_OUTPUT";
--    variable ll   : LINE;
--    begin
--        write( ll , str );
--        writeline(FSTR, ll);
--    end printf;
--
    procedure printnewtest( str : STRING) is
    begin
        printf("-----------------------------------------------------");
        printf(str);
    end printnewtest;

    procedure printpass ( passc : passcheck ) is
	variable passflag : integer;
    begin
	passflag := 1;
	for i in 0 to passc.n loop
		if passc.result(i) = 0 then
			passflag := 0;
		end if;
	end loop;
        printf("-----------------------------------------------------");
        printf("-----------------------------------------------------");
	if passflag = 1 then
		printf("ALL TESTS ARE PASSED");
	else
		printf("ONE OR MORE TESTS ARE FAILED");
	end if;
        printf("-----------------------------------------------------");
        printf("-----------------------------------------------------");
    end printpass;

    procedure printerror(ERR  : inout BOOLEAN;
                         str  : STRING) is
    variable str1 : STRING ( 1 to 40);
    file FSTR : TEXT is out "STD_OUTPUT";
    variable ll   : LINE;
    begin
       ERR  := TRUE;
       str1(1 to 7) := "ERROR: ";
       for i in str'range loop
           str1(i+7) := str(i);
       end loop;
       write( ll , str1 );
       writeline(FSTR, ll);
       assert FALSE
         report "ERROR OCCURED"
         severity ERROR;  
    end printerror;


    ------------------------------------------------------------------
    -- Misc Type conversions   
    --       


    function to_logic( x : boolean) return std_logic is
    begin
       if x then 
       return('1');
       else
       return('0');
       end if;
    end to_logic;

    function to_boolean( x : std_logic) return boolean is
    begin
       if to_X01(x)='1' then 
          return(TRUE);
       else
          return(FALSE);
       end if;
    end to_boolean;

    procedure waitclocks( N   : in INTEGER;
                         signal clk : in std_logic) is
    begin
      for i in 1 to N loop
         wait until clk'event and clk='1';
      end loop;
    end waitclocks;

    ------------------------------------------------------------------
    -- basic CPU read and write cycles 
    --       


    procedure cpu_write(N       : in  INTEGER range 1 to 2;
                        data    : in  std_logic_vector;
                        signal  clk     : in  std_logic;
                        signal  control : out Tcpucontrol ) is 
    begin
         case N is 
           when 1 =>  control.sel1  <= '0';
           when 2 =>  control.sel2  <= '0';
         end case;
       control.OEn <= '1';
       control.data  <= data;
       control.WEn   <= '0';
       waitclocks(1,clk);
       control.WEn   <= '1';