📄 testbnch.vhd
字号:
WAIT FOR 0 ns;
END LOOP;
END IF;
IF ((FIXEDMODE = 0) OR ((PRG_BIT8 = 0) AND (PRG_PARITY = 2))) THEN
WRITE("Setting UART1 7bit, parity enabled, and even parity") ;
-- UART1 7bit, parity enabled, and even parity
wdata1 <= "00000010";
cpu_write1("000001100", wdata1);
WRITE("Setting UART2 7bit, parity enabled, and odd parity");
-- UART2 7bit, parity enabled, and odd parity
wdata2 <= "00000110";
cpu_write2("000001100", wdata2);
FOR X IN 1 TO 10 LOOP
WAIT UNTIL (PCLK'EVENT AND PCLK = '1');
END LOOP;
IF (FIFO_DEPTH_16 = 1) THEN
count <= "000010000";
ELSE
count <= "010000000";
END IF;
WRITE("Testing parity error generation");
-- Initialiase test data
tc <= "000000000";
rc <= "000000000";
i <= "000000000";
i <= "000000000";
WAIT FOR 0 ns;
WHILE (i<=count - "000000001") LOOP
tdata(to_integer(i)) <= i(7 DOWNTO 0);
par_err(to_integer(i)) <= "00000000";
i <= i + "000000001";
WAIT FOR 0 ns;
END LOOP;
WHILE (rc < count) LOOP
WAIT UNTIL (PCLK'EVENT AND PCLK = '1');
IF (tc < count) THEN
-- Firstly See if the Transmitter is ready
IF (UARTstatus1_txrdy = '1') THEN
wdata <= tdata(to_integer(tc));
cpu_write1("000000000", wdata);
tc <= tc + "000000001";
END IF;
END IF;
IF (RX_FIFO = 0) THEN
-- Now See if any received data
IF (UARTstatus2_rxrdy = '1') THEN
par_err(to_integer(rc)) <= "0000000" &
UARTstatus2_parity_err;
cpu_read2("000000100");
rdata(to_integer(rc)) <= UARTstatus2_data_out;
rc <= rc + "000000001";
END IF;
ELSE
IF (UARTstatus2_parity_err = '1') THEN
par_err(to_integer(rc)) <= "0000000" &
UARTstatus2_parity_err;
cpu_read2("000000100");
rdata(to_integer(rc)) <= UARTstatus2_data_out;
rc <= rc + "000000001";
END IF;
END IF;
END LOOP;
passflag <= "000000000";
i <= "000000000";
WAIT FOR 0 ns;
WHILE (i<=count - "000000001") LOOP
IF (par_err(to_integer(i)) /= "00000001") THEN
WRITE("THIS TEST IS FAILED");
ASSERT (FALSE) REPORT "'$finish' Encountered" SEVERITY
FAILURE;
ELSE
passflag <= passflag + "000000001";
IF (passflag = count) THEN
WRITE("THIS TEST IS PASSED");
WRITE("-----------------------------------------------------");
END IF;
END IF;
i <= i + "000000001";
WAIT FOR 0 ns;
END LOOP;
END IF;
IF ((FIXEDMODE = 0) OR ((PRG_BIT8 = 0) AND (PRG_PARITY = 1))) THEN
WRITE("Setting UART1 7bit, parity enabled, and odd parity");
-- UART1 7bit, parity enabled, and odd parity
wdata1 <= "00000110";
cpu_write1("000001100", wdata1);
WRITE("Setting UART2 8bit, parity enabled, and even parity") ;
-- UART2 7bit, parity enabled, and even parity
wdata2 <= "00000010";
cpu_write2("000001100", wdata2);
FOR X IN 1 TO 10 LOOP
WAIT UNTIL (PCLK'EVENT AND PCLK = '1');
END LOOP;
IF (FIFO_DEPTH_16 = 1) THEN
count <= "000010000";
ELSE
count <= "100000000";
END IF;
WRITE("Testing parity error generation");
-- Initialiase test data
tc <= "000000000";
rc <= "000000000";
i <= "000000000";
i <= "000000000";
WAIT FOR 0 ns;
WHILE (i<=count - "000000001") LOOP
tdata(to_integer(i)) <= i(7 DOWNTO 0);
par_err(to_integer(i)) <= "00000000";
i <= i + "000000001";
WAIT FOR 0 ns;
END LOOP;
WHILE (rc < count) LOOP
WAIT UNTIL (PCLK'EVENT AND PCLK = '1');
IF (tc < count) THEN
-- Firstly See if the Transmitter is ready
IF (UARTstatus1_txrdy = '1') THEN
wdata <= tdata(to_integer(tc));
cpu_write1("000000000", wdata);
tc <= tc + "000000001";
END IF;
END IF;
IF (RX_FIFO = 0) THEN
-- Now See if any received data
IF (UARTstatus2_rxrdy = '1') THEN
par_err(to_integer(rc)) <= "0000000" &
UARTstatus2_parity_err;
cpu_read2("000000100");
rdata(to_integer(rc)) <= UARTstatus2_data_out;
rc <= rc + "000000001";
END IF;
ELSE
IF (UARTstatus2_parity_err = '1') THEN
par_err(to_integer(rc)) <= "0000000" &
UARTstatus2_parity_err;
cpu_read2("000000100");
rdata(to_integer(rc)) <= UARTstatus2_data_out;
rc <= rc + "000000001";
END IF;
END IF;
END LOOP;
passflag <= "000000000";
i <= "000000000";
WAIT FOR 0 ns;
WHILE (i<=count - "000000001") LOOP
IF (par_err(to_integer(i)) /= "00000001") THEN
WRITE("THIS TEST IS FAILED");
ASSERT (FALSE) REPORT "'$finish' Encountered" SEVERITY
FAILURE;
ELSE
passflag <= passflag + "000000001";
IF (passflag = count) THEN
WRITE("THIS TEST IS PASSED");
WRITE("-----------------------------------------------------");
END IF;
END IF;
i <= i + "000000001";
WAIT FOR 0 ns;
END LOOP;
END IF;
-----------------------------------
-- Testing Overflow circuitry
-----------------------------------
IF ((FIXEDMODE = 0) OR ((PRG_BIT8 = 1) AND (PRG_PARITY = 1))) THEN
IF (RX_FIFO = 0) THEN
WRITE("Setting UART1 8bit, parity enabled, and odd parity");
wdata1 <= "00000011";
cpu_write1("000001100", wdata1);
WRITE("Setting UART2 8bit, parity enabled, and odd parity");
wdata2 <= "00000011";
cpu_write2("000001100", wdata2);
FOR X IN 1 TO 100 LOOP
WAIT UNTIL (PCLK'EVENT AND PCLK = '1');
END LOOP;
WRITE("Testing for RX data overflow");
cpu_write1("000000000", "10100101");
FOR X IN 1 TO 5 LOOP
WAIT UNTIL (PCLK'EVENT AND PCLK = '1');
END LOOP;
IF (UARTstatus2_overflow = '1') THEN
WRITE("Overflow set too early");
END IF;
IF (UARTstatus1_txrdy = '1') THEN
cpu_write1("000000000", "01011010");
WAIT UNTIL (UARTstatus2_overflow'EVENT AND
UARTstatus2_overflow = '1');
FOR X IN 1 TO 10 LOOP
WAIT UNTIL (PCLK'EVENT AND PCLK = '1');
END LOOP;
ELSE
WAIT UNTIL (UARTstatus1_txrdy'EVENT AND
UARTstatus1_txrdy = '1');
FOR X IN 1 TO 10 LOOP
WAIT UNTIL (PCLK'EVENT AND PCLK = '1');
END LOOP;
cpu_write1("000000000", "01011010");
WAIT UNTIL (UARTstatus2_overflow'EVENT AND
UARTstatus2_overflow = '1');
FOR X IN 1 TO 10 LOOP
WAIT UNTIL (PCLK'EVENT AND PCLK = '1');
END LOOP;
END IF;
-- Get the byte, should be the first one
IF (UARTstatus2_rxrdy = '1') THEN
cpu_read2("000000100");
ELSE
WAIT UNTIL (UARTstatus2_rxrdy'EVENT AND
UARTstatus2_rxrdy = '1');
cpu_read2("000000100");
END IF;
IF (UARTstatus2_data_out /= "10100101") THEN
WRITE("THIS TEST IS FAILED");
ASSERT (FALSE) REPORT "'$finish' Encountered" SEVERITY
FAILURE;
ELSE
WRITE("THIS TEST IS PASSED");
WRITE("-----------------------------------------------------");
END IF;
FOR X IN 1 TO 5 LOOP
WAIT UNTIL (PCLK'EVENT AND PCLK = '1');
END LOOP;
cpu_write1("000000000", "01011010");
END IF;
END IF;
IF ((FIXEDMODE = 0) OR ((PRG_BIT8 = 1) AND (PRG_PARITY = 2))) THEN
IF (RX_FIFO = 1) THEN
WRITE("Setting UART1 Operating Mode 8 bit, parity enabled, and even parity");
wdata1 <= "00000011";
cpu_write1("000001100", wdata1);
WRITE("Setting UART2 Operating Mode 8 bit, parity enabled, and even parity");
wdata2 <= "00000011";
cpu_write2("000001100", wdata2);
FOR X IN 1 TO 10 LOOP
WAIT UNTIL (PCLK'EVENT AND PCLK = '1');
END LOOP;
IF (FIFO_DEPTH_16 = 1) THEN
count <= "000010000";
ELSE
count <= "100000000";
END IF;
tc <= "000000000";
rc <= "000000000";
WRITE("Testing for RX data overflow");
-- Initialiase test data
i <= "000000000";
WAIT FOR 0 ns;
WHILE (i<=count - "000000001") LOOP
tdata(to_integer(i)) <= i(7 DOWNTO 0);
i <= i + "000000001";
WAIT FOR 0 ns;
END LOOP;
WHILE (tc < count) LOOP
WAIT UNTIL (PCLK'EVENT AND PCLK = '1');
IF (tc < count) THEN
-- Firstly See if the Transmitter is ready
IF (UARTstatus1_txrdy = '1') THEN
wdata <= tdata(to_integer(tc));
cpu_write1("000000000", wdata);
tc <= tc + "000000001";
END IF;
END IF;
END LOOP;
WAIT UNTIL (UARTstatus2_overflow'EVENT AND
UARTstatus2_overflow = '1');
-- Now See if any received data
cpu_read2("000000100");
rdata(0) <= UARTstatus2_data_out;
-- END IF;
-- Verify that correct data received
IF (rdata(0) /= tdata(0)) THEN
WRITE("THIS TEST IS FAILED");
ASSERT (FALSE) REPORT "'$finish' Encountered" SEVERITY
FAILURE;
ELSE
WRITE("THIS TEST IS PASSED");
WRITE("-----------------------------------------------------");
END IF;
END IF;
END IF;
WRITE("END OF SIMULATION");
WRITE("ALL TESTS ARE PASSED");
ASSERT (FALSE) REPORT "'$finish' Encountered" SEVERITY FAILURE;
xhdl_initial := FALSE;
ELSE
WAIT;
END IF;
END PROCESS xhdl_7;
END ARCHITECTURE translated;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -