📄 testbnch.vhd
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IF (rdata(to_integer(i)) /= tdata(to_integer(i))) THEN
WRITE("THIS TEST IS FAILED");
ASSERT (FALSE) REPORT "'$finish' Encountered" SEVERITY
FAILURE;
ELSE
passflag <= passflag + "000000001";
IF (passflag = count) THEN
WRITE("THIS TEST IS PASSED");
WRITE("-----------------------------------------------------");
END IF;
END IF;
i <= i + "000000001";
WAIT FOR 0 ns;
END LOOP;
END IF;
IF ((FIXEDMODE = 0) OR ((PRG_BIT8 = 1) AND (PRG_PARITY = 0))) THEN
WRITE("Setting UART1 Operating Mode 8 bit, parity disabled") ;
wdata1 <= "00000101";
cpu_write1("000001100", wdata1);
WRITE("Setting UART2 Operating Mode 8 bit, parity disabled") ;
wdata2 <= "00000101";
cpu_write2("000001100", wdata2);
FOR X IN 1 TO 10 LOOP
WAIT UNTIL (PCLK'EVENT AND PCLK = '1');
END LOOP;
IF (FIFO_DEPTH_16 = 1) THEN
count <= "000010000";
ELSE
count <= "100000000";
END IF;
tc <= "000000000";
rc <= "000000000";
WRITE("Testing Continuous Data Stream UART1 to UART2");
-- Initialiase test data
i <= "000000000";
WAIT FOR 0 ns;
WHILE (i<=count - "000000001") LOOP
tdata(to_integer(i)) <= i(7 DOWNTO 0);
i <= i + "000000001";
WAIT FOR 0 ns;
END LOOP;
WHILE (rc < count) LOOP
WAIT UNTIL (PCLK'EVENT AND PCLK = '1');
IF (tc < count) THEN
-- Firstly See if the Transmitter is ready
IF (UARTstatus1_txrdy = '1') THEN
wdata <= tdata(to_integer(tc));
cpu_write1("000000000", wdata);
tc <= tc + "000000001";
END IF;
END IF;
-- Now See if any received data
IF (UARTstatus2_rxrdy = '1') THEN
cpu_read2("000000100");
rdata(to_integer(rc)) <= UARTstatus2_data_out;
rc <= rc + "000000001";
END IF;
END LOOP;
-- Verify that correct data received
passflag <= "000000000";
i <= "000000000";
WAIT FOR 0 ns;
WHILE (i<=count - "000000001") LOOP
IF (rdata(to_integer(i)) /= tdata(to_integer(i))) THEN
WRITE("THIS TEST IS FAILED");
ASSERT (FALSE) REPORT "'$finish' Encountered" SEVERITY
FAILURE;
ELSE
passflag <= passflag + "000000001";
IF (passflag = count) THEN
WRITE("THIS TEST IS PASSED");
WRITE("-----------------------------------------------------");
END IF;
END IF;
i <= i + "000000001";
WAIT FOR 0 ns;
END LOOP;
END IF;
IF ((FIXEDMODE = 0) OR ((PRG_BIT8 = 0) AND (PRG_PARITY = 0))) THEN
WRITE("Setting UART1 Operating Mode 7 bit, parity disabled") ;
wdata1 <= "00000100";
cpu_write1("000001100", wdata1);
WRITE("Setting UART2 Operating Mode 7 bit, parity disabled") ;
wdata2 <= "00000100";
cpu_write2("000001100", wdata2);
FOR X IN 1 TO 10 LOOP
WAIT UNTIL (PCLK'EVENT AND PCLK = '1');
END LOOP;
IF (FIFO_DEPTH_16 = 1) THEN
count <= "000010000";
ELSE
count <= "010000000";
END IF;
tc <= "000000000";
rc <= "000000000";
WRITE("Testing Continuous Data Stream UART1 to UART2");
-- Initialiase test data
i <= "000000000";
WAIT FOR 0 ns;
WHILE (i<=count - "000000001") LOOP
tdata(to_integer(i)) <= i(7 DOWNTO 0);
i <= i + "000000001";
WAIT FOR 0 ns;
END LOOP;
WHILE (rc < count) LOOP
WAIT UNTIL (PCLK'EVENT AND PCLK = '1');
IF (tc < count) THEN
-- Firstly See if the Transmitter is ready
IF (UARTstatus1_txrdy = '1') THEN
wdata <= tdata(to_integer(tc));
cpu_write1("000000000", wdata);
tc <= tc + "000000001";
END IF;
END IF;
-- Now See if any received data
IF (UARTstatus2_rxrdy = '1') THEN
cpu_read2("000000100");
rdata(to_integer(rc)) <= UARTstatus2_data_out;
rc <= rc + "000000001";
END IF;
END LOOP;
-- Verify that correct data received
passflag <= "000000000";
i <= "000000000";
WAIT FOR 0 ns;
WHILE (i<=count - "000000001") LOOP
IF (rdata(to_integer(i)) /= tdata(to_integer(i))) THEN
WRITE("THIS TEST IS FAILED");
ASSERT (FALSE) REPORT "'$finish' Encountered" SEVERITY
FAILURE;
ELSE
passflag <= passflag + "000000001";
IF (passflag = count) THEN
WRITE("THIS TEST IS PASSED");
WRITE("-----------------------------------------------------");
END IF;
END IF;
i <= i + "000000001";
WAIT FOR 0 ns;
END LOOP;
END IF;
-----------------------------------
-- Testing PARITY ERROR Generations
-----------------------------------
IF ((FIXEDMODE = 0) OR ((PRG_BIT8 = 1) AND (PRG_PARITY = 2))) THEN
WRITE("Setting UART1 8bit, parity enabled, and even parity") ;
-- UART1 8bit, parity enabled, and even parity
wdata1 <= "00000011";
cpu_write1("000001100", wdata1);
WRITE("Setting UART2 8bit, parity enabled, and odd parity");
wdata2 <= "00000111";
cpu_write2("000001100", wdata2);
-- UART2 8bit, parity enabled, and odd parity
FOR X IN 1 TO 10 LOOP
WAIT UNTIL (PCLK'EVENT AND PCLK = '1');
END LOOP;
IF (FIFO_DEPTH_16 = 1) THEN
count <= "000010000";
ELSE
count <= "100000000";
END IF;
WRITE("Testing parity error generation");
-- Initialiase test data
tc <= "000000000";
rc <= "000000000";
i <= "000000000";
i <= "000000000";
WAIT FOR 0 ns;
WHILE (i<=count - "000000001") LOOP
tdata(to_integer(i)) <= i(7 DOWNTO 0);
par_err(to_integer(i)) <= "00000000";
i <= i + "000000001";
WAIT FOR 0 ns;
END LOOP;
WHILE (rc < count) LOOP
WAIT UNTIL (PCLK'EVENT AND PCLK = '1');
IF (tc < count) THEN
-- Firstly See if the Transmitter is ready
IF (UARTstatus1_txrdy = '1') THEN
wdata <= tdata(to_integer(tc));
cpu_write1("000000000", wdata);
tc <= tc + "000000001";
END IF;
END IF;
IF (RX_FIFO = 0) THEN
-- Now See if any received data
IF (UARTstatus2_rxrdy = '1') THEN
par_err(to_integer(rc)) <= "0000000" &
UARTstatus2_parity_err;
cpu_read2("000000100");
rdata(to_integer(rc)) <= UARTstatus2_data_out;
rc <= rc + "000000001";
END IF;
ELSE
IF (UARTstatus2_parity_err = '1') THEN
par_err(to_integer(rc)) <= "0000000" &
UARTstatus2_parity_err;
cpu_read2("000000100");
rdata(to_integer(rc)) <= UARTstatus2_data_out;
rc <= rc + "000000001";
END IF;
END IF;
END LOOP;
passflag <= "000000000";
i <= "000000000";
WAIT FOR 0 ns;
WHILE (i<=count - "000000001") LOOP
IF (par_err(to_integer(i)) /= "00000001") THEN
WRITE("THIS TEST IS FAILED");
ASSERT (FALSE) REPORT "'$finish' Encountered" SEVERITY
FAILURE;
ELSE
passflag <= passflag + "000000001";
IF (passflag = count) THEN
WRITE("THIS TEST IS PASSED");
WRITE("-----------------------------------------------------");
END IF;
END IF;
i <= i + "000000001";
WAIT FOR 0 ns;
END LOOP;
END IF;
IF ((FIXEDMODE = 0) OR ((PRG_BIT8 = 1) AND (PRG_PARITY = 1))) THEN
WRITE("Setting UART1 8bit, parity enabled, and odd parity");
-- UART1 8bit, parity enabled, and odd parity
wdata1 <= "00000111";
cpu_write1("000001100", wdata1);
WRITE("Setting UART2 8bit, parity enabled, and even parity") ;
wdata2 <= "00000011";
cpu_write2("000001100", wdata2);
FOR X IN 1 TO 10 LOOP
WAIT UNTIL (PCLK'EVENT AND PCLK = '1');
END LOOP;
IF (FIFO_DEPTH_16 = 1) THEN
count <= "000010000";
ELSE
count <= "100000000";
END IF;
WRITE("Testing parity error generation");
-- Initialiase test data
tc <= "000000000";
rc <= "000000000";
i <= "000000000";
i <= "000000000";
WAIT FOR 0 ns;
WHILE (i<=count - "000000001") LOOP
tdata(to_integer(i)) <= i(7 DOWNTO 0);
par_err(to_integer(i)) <= "00000000";
i <= i + "000000001";
WAIT FOR 0 ns;
END LOOP;
WHILE (rc < count) LOOP
WAIT UNTIL (PCLK'EVENT AND PCLK = '1');
IF (tc < count) THEN
-- Firstly See if the Transmitter is ready
IF (UARTstatus1_txrdy = '1') THEN
wdata <= tdata(to_integer(tc));
cpu_write1("000000000", wdata);
tc <= tc + "000000001";
END IF;
END IF;
IF (RX_FIFO = 0) THEN
-- Now See if any received data
IF (UARTstatus2_rxrdy = '1') THEN
par_err(to_integer(rc)) <= "0000000" &
UARTstatus2_parity_err;
cpu_read2("000000100");
rdata(to_integer(rc)) <= UARTstatus2_data_out;
rc <= rc + "000000001";
END IF;
ELSE
IF (UARTstatus2_parity_err = '1') THEN
par_err(to_integer(rc)) <= "0000000" &
UARTstatus2_parity_err;
cpu_read2("000000100");
rdata(to_integer(rc)) <= UARTstatus2_data_out;
rc <= rc + "000000001";
END IF;
END IF;
END LOOP;
passflag <= "000000000";
i <= "000000000";
WAIT FOR 0 ns;
WHILE (i<=count - "000000001") LOOP
IF (par_err(to_integer(i)) /= "00000001") THEN
WRITE("THIS TEST IS FAILED");
ASSERT (FALSE) REPORT "'$finish' Encountered" SEVERITY
FAILURE;
ELSE
passflag <= passflag + "000000001";
IF (passflag = count) THEN
WRITE("THIS TEST IS PASSED");
WRITE("-----------------------------------------------------");
END IF;
END IF;
i <= i + "000000001";
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