📄 testbnch.vhd
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PWRITE1 <= '1';
WAIT UNTIL (PCLK'EVENT AND PCLK = '0');
PENABLE1 <= '0';
PSEL1 <= '1';
PADDR1 <= address;
PWRITE1 <= '0';
WAIT UNTIL (PCLK'EVENT AND PCLK = '0');
PENABLE1 <= '1';
WAIT UNTIL (PCLK'EVENT AND PCLK = '0');
PWRITE1 <= '1';
PENABLE1 <= '0';
PSEL1 <= '0';
-- $display("CPU Read %04x",address);
END PROCEDURE cpu_read1;
PROCEDURE WRITE (
val : IN string) IS
VARIABLE ptr : line;
BEGIN
WRITE(OUTPUT, val);
WRITELINE(OUTPUT, ptr);
END WRITE;
BEGIN
IF (xhdl_initial) THEN
-- ALL TESTS BY DEFAULT TRANSMIT ON UART1 AND RECEIVE ON UART2
WRITE("Actel UART Testbench v3.00 ");
WRITE("--------------------------------------");
WRITE(" ");
------------------------------------
-- initial control signal conditions
------------------------------------
PSEL1 <= '0';
PSEL2 <= '0';
PWDATA1 <= "00000000";
-------------------------------------------------
-- drive the resets
-------------------------------------------------
WRITE("Appling Reset");
PRESETN <= '0';
FOR X IN 1 TO 10 LOOP
WAIT UNTIL (PCLK'EVENT AND PCLK = '1');
END LOOP;
WAIT UNTIL (PCLK'EVENT AND PCLK = '1');
WAIT FOR 100 * xhdl_timescale;
PRESETN <= '1';
IF ((FIXEDMODE = 0) OR ((PRG_BIT8 = 1) AND (PRG_PARITY = 2) )) THEN
WRITE("Setting UART1 Operating Mode 8 bit, parity enabled, and even parity");
wdata1 <= "00000011";
cpu_write1("000001100", wdata1);
WRITE("Setting UART2 Operating Mode 8 bit, parity enabled, and even parity");
wdata2 <= "00000011";
cpu_write2("000001100", wdata2);
FOR X IN 1 TO 10 LOOP
WAIT UNTIL (PCLK'EVENT AND PCLK = '1');
END LOOP;
IF (FIFO_DEPTH_16 = 1) THEN
count <= "000010000";
ELSE
count <= "100000000";
END IF;
tc <= "000000000";
rc <= "000000000";
WRITE("Testing Continuous Data Stream UART1 to UART2");
-- Initialiase test data
i <= "000000000";
WAIT FOR 0 ns;
WHILE (i<=count - "000000001") LOOP
tdata(to_integer(i)) <= i(7 DOWNTO 0);
i <= i + "000000001";
WAIT FOR 0 ns;
END LOOP;
WHILE (rc < count) LOOP
WAIT UNTIL (PCLK'EVENT AND PCLK = '1');
IF (tc < count) THEN
-- Firstly See if the Transmitter is ready
IF (UARTstatus1_txrdy = '1') THEN
wdata <= tdata(to_integer(tc));
cpu_write1("000000000", wdata);
tc <= tc + "000000001";
END IF;
END IF;
-- Now See if any received data
IF (UARTstatus2_rxrdy = '1') THEN
cpu_read2("000000100");
rdata(to_integer(rc)) <= UARTstatus2_data_out;
rc <= rc + "000000001";
END IF;
END LOOP;
-- Verify that correct data received
passflag <= "000000000";
i <= "000000000";
WAIT FOR 0 ns;
WHILE (i<=count - "000000001") LOOP
IF (rdata(to_integer(i)) /= tdata(to_integer(i))) THEN
WRITE("THIS TEST IS FAILED");
ASSERT (FALSE) REPORT "'$finish' Encountered" SEVERITY
FAILURE;
ELSE
-- $display("CPU write data %04x",tdata[i]);
-- $display("CPU read data %04x",rdata[i]);
passflag <= passflag + "000000001";
IF (passflag = count) THEN
WRITE("THIS TEST IS PASSED");
WRITE("-----------------------------------------------------");
END IF;
END IF;
i <= i + "000000001";
WAIT FOR 0 ns;
END LOOP;
END IF;
IF ((FIXEDMODE = 0) OR ((PRG_BIT8 = 1) AND (PRG_PARITY = 1))) THEN
WRITE("Setting UART1 Operating Mode 8 bit, parity enabled, and odd parity");
wdata1 <= "00000111";
cpu_write1("000001100", wdata1);
WRITE("Setting UART2 Operating Mode 8 bit, parity enabled, and odd parity");
wdata2 <= "00000111";
cpu_write2("000001100", wdata2);
FOR X IN 1 TO 10 LOOP
WAIT UNTIL (PCLK'EVENT AND PCLK = '1');
END LOOP;
IF (FIFO_DEPTH_16 = 1) THEN
count <= "000010000";
ELSE
count <= "100000000";
END IF;
tc <= "000000000";
rc <= "000000000";
WRITE("Testing Continuous Data Stream UART1 to UART2");
-- Initialiase test data
i <= "000000000";
WAIT FOR 0 ns;
WHILE (i<=count - "000000001") LOOP
tdata(to_integer(i)) <= i(7 DOWNTO 0);
i <= i + "000000001";
WAIT FOR 0 ns;
END LOOP;
WHILE (rc < count) LOOP
WAIT UNTIL (PCLK'EVENT AND PCLK = '1');
IF (tc < count) THEN
-- Firstly See if the Transmitter is ready
IF (UARTstatus1_txrdy = '1') THEN
wdata <= tdata(to_integer(tc));
cpu_write1("000000000", wdata);
tc <= tc + "000000001";
END IF;
END IF;
-- Now See if any received data
IF (UARTstatus2_rxrdy = '1') THEN
cpu_read2("000000100");
rdata(to_integer(rc)) <= UARTstatus2_data_out;
rc <= rc + "000000001";
END IF;
END LOOP;
-- Verify that correct data received
passflag <= "000000000";
i <= "000000000";
WAIT FOR 0 ns;
WHILE (i<=count - "000000001") LOOP
IF (rdata(to_integer(i)) /= tdata(to_integer(i))) THEN
WRITE("THIS TEST IS FAILED");
ASSERT (FALSE) REPORT "'$finish' Encountered" SEVERITY
FAILURE;
ELSE
passflag <= passflag + "000000001";
IF (passflag = count) THEN
WRITE("THIS TEST IS PASSED");
WRITE("-----------------------------------------------------");
END IF;
END IF;
i <= i + "000000001";
WAIT FOR 0 ns;
END LOOP;
END IF;
IF ((FIXEDMODE = 0) OR ((PRG_BIT8 = 0) AND (PRG_PARITY = 2))) THEN
WRITE("Setting UART1 Operating Mode 7 bit, parity enabled, and even parity");
wdata1 <= "00000010";
cpu_write1("000001100", wdata1);
WRITE("Setting UART2 Operating Mode 7 bit, parity enabled, and even parity");
wdata2 <= "00000010";
cpu_write2("000001100", wdata2);
FOR X IN 1 TO 10 LOOP
WAIT UNTIL (PCLK'EVENT AND PCLK = '1');
END LOOP;
IF (FIFO_DEPTH_16 = 1) THEN
count <= "000010000";
ELSE
count <= "010000000";
END IF;
tc <= "000000000";
rc <= "000000000";
WRITE("Testing Continuous Data Stream UART1 to UART2");
-- Initialiase test data
i <= "000000000";
WAIT FOR 0 ns;
WHILE (i<=count - "000000001") LOOP
tdata(to_integer(i)) <= i(7 DOWNTO 0);
i <= i + "000000001";
WAIT FOR 0 ns;
END LOOP;
WHILE (rc < count) LOOP
WAIT UNTIL (PCLK'EVENT AND PCLK = '1');
IF (tc < count) THEN
-- Firstly See if the Transmitter is ready
IF (UARTstatus1_txrdy = '1') THEN
wdata <= tdata(to_integer(tc));
cpu_write1("000000000", wdata);
tc <= tc + "000000001";
END IF;
END IF;
-- Now See if any received data
IF (UARTstatus2_rxrdy = '1') THEN
cpu_read2("000000100");
rdata(to_integer(rc)) <= UARTstatus2_data_out;
rc <= rc + "000000001";
END IF;
END LOOP;
-- Verify that correct data received
passflag <= "000000000";
i <= "000000000";
WAIT FOR 0 ns;
WHILE (i<=count - "000000001") LOOP
IF (rdata(to_integer(i)) /= tdata(to_integer(i))) THEN
WRITE("THIS TEST IS FAILED");
ASSERT (FALSE) REPORT "'$finish' Encountered" SEVERITY
FAILURE;
ELSE
passflag <= passflag + "000000001";
IF (passflag = count) THEN
WRITE("THIS TEST IS PASSED");
WRITE("-----------------------------------------------------");
END IF;
END IF;
i <= i + "000000001";
WAIT FOR 0 ns;
END LOOP;
END IF;
IF ((FIXEDMODE = 0) OR ((PRG_BIT8 = 0) AND (PRG_PARITY = 1))) THEN
WRITE("Setting UART1 Operating Mode 7 bit, parity enabled, and odd parity");
wdata1 <= "00000110";
cpu_write1("000001100", wdata1);
WRITE("Setting UART2 Operating Mode 7 bit, parity enabled, and odd parity");
wdata2 <= "00000110";
cpu_write2("000001100", wdata2);
FOR X IN 1 TO 10 LOOP
WAIT UNTIL (PCLK'EVENT AND PCLK = '1');
END LOOP;
IF (FIFO_DEPTH_16 = 1) THEN
count <= "000010000";
ELSE
count <= "010000000";
END IF;
tc <= "000000000";
rc <= "000000000";
WRITE("Testing Continuous Data Stream UART1 to UART2");
-- Initialiase test data
i <= "000000000";
WAIT FOR 0 ns;
WHILE (i<=count - "000000001") LOOP
tdata(to_integer(i)) <= i(7 DOWNTO 0);
i <= i + "000000001";
WAIT FOR 0 ns;
END LOOP;
WHILE (rc < count) LOOP
WAIT UNTIL (PCLK'EVENT AND PCLK = '1');
IF (tc < count) THEN
-- Firstly See if the Transmitter is ready
IF (UARTstatus1_txrdy = '1') THEN
wdata <= tdata(to_integer(tc));
cpu_write1("000000000", wdata);
tc <= tc + "000000001";
END IF;
END IF;
-- Now See if any received data
IF (UARTstatus2_rxrdy = '1') THEN
cpu_read2("000000100");
rdata(to_integer(rc)) <= UARTstatus2_data_out;
rc <= rc + "000000001";
END IF;
END LOOP;
-- Verify that correct data received
passflag <= "000000000";
i <= "000000000";
WAIT FOR 0 ns;
WHILE (i<=count - "000000001") LOOP
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