testbnch.vhd

Actel Fusion System Management Development Kit UART Example. Contains Libero design using CoreABC. P

-- ------------------------------------------------------------------------- --
-- ------------------------------------------------------------------------- --
--                                                                           --
-- File................: TESTBNCH.V                                        --
-- Function............: Test bench for GENERIC UARTapb                          --
-- Version.............: 3.1                                                --
-- Last Updated........: 03-08-07                                            --
-- Component of........: None                                                --
-- Components Required.: UARTapb                                                 --
-- Compilation Notes...:                                                     --
--                                                                           --
-- Revision History:                                                         --
--   3.1:   Coreconsole version along with APB interface testbench
--   3.00:  added fifo verification
--   2.00:  improve report
--   1.01:  Initial design                                                   --
--   1.00:  Initial design                                                   --
--                                                                           --
--                                                                           --
-- ------------------------------------------------------------------------- --
-- ------------------------------------------------------------------------- --
library ieee;
library std;
use ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
LIBRARY std;
use std.textio.all;
use work.tbpack.all;
use work.textio.all;
use work.misc.all;
use work.coreparameters.all;

ENTITY testbnch IS
   GENERIC (
      --  0=without fifo operation mode
      TX_FIFO                        :  integer := 0;    
      --  0=without fifo operation mode
      RX_FIFO                        :  integer := 0;    
      --  0=fifo depth is 256 bytes for devices
      --  (PA3/E, APA, AX, RTAX-S)
      -- DEVICE FAMILY 
      FAMILY                         :  integer := 15;    
      --  1=fifo depth is 16 bytes, FIFO_DEPTH_16
      --  is used for the testbench purpose only to
      --  support the devices(SX-A, RTSX-S)
      BAUD_VALUE                     :  integer := 1;    --  This value is selected only when FIXEDMODE is set to 1 
      FIXEDMODE                      :  integer := 0;    --  fixed or programmable mode, 0: programmable; 1:fixed
      PRG_BIT8                     :  integer := 0;    --  This bit value is selected only when FIXEDMODE is set to 1 
      PRG_PARITY                   :  integer := 0;    --  This value is selected only when FIXEDMODE is set to 1 
      -- The following parameter is used only in the testbench
      FIFO_DEPTH_16                  :  integer := 0);    
 END ENTITY testbnch;

ARCHITECTURE translated OF testbnch IS

COMPONENT CoreUARTapb 
   GENERIC (
      -- DEVICE FAMILY 
      FAMILY                         :  integer := 15;    
      -- UART configuration parameters
      TX_FIFO                        :  integer := 0;    --  1 = with tx fifo, 0 = without tx fifo
      RX_FIFO                        :  integer := 0;    --  1 = with rx fifo, 0 = without rx fifo
      BAUD_VALUE                     :  integer := 0;    --  Baud value is set only when fixed buad rate is selected 
      FIXEDMODE                      :  integer := 0;    --  fixed or programmable mode, 0: programmable; 1:fixed
      PRG_BIT8                       :  integer := 0;    --  This bit value is selected only when FIXEDMODE is set to 1 
      PRG_PARITY                     :  integer := 0);    --  This bit value is selected only when FIXEDMODE is set to 1 
   PORT (
      -- Inputs and Outputs
-- APB signals

      PCLK                    : IN std_logic;   --  APB system clock
      PRESETN                 : IN std_logic;   --  APB system reset
      PADDR                   : IN std_logic_vector(4 DOWNTO 2);   --  Address (used bits only)
      PSEL                    : IN std_logic;   --  Peripheral select signal
      PENABLE                 : IN std_logic;   --  Enable (data valid strobe)
      PWRITE                  : IN std_logic;   --  Write/nRead signal
      PWDATA                  : IN std_logic_vector(7 DOWNTO 0);   --  8 bit write data
      PRDATA                  : OUT std_logic_vector(7 DOWNTO 0);   --  8 bit read data
      -- transmit ready and receive full indicators

      TXRDY                   : OUT std_logic;   
      RXRDY                   : OUT std_logic;   
      -- FLAGS 

      PARITY_ERR              : OUT std_logic;   
      OVERFLOW                : OUT std_logic;   
      -- Serial receive and transmit data

      RX                      : IN std_logic;   
      TX                      : OUT std_logic);   
END COMPONENT ;

   CONSTANT xhdl_timescale         : time := 1 ns;

   TYPE xhdl_1 IS ARRAY (0 TO 511) OF std_logic_vector(7 DOWNTO 0);



   -------------------------------------------------
   -- component port listings
   -------------------------------------------------
   --  1=with fifo operation mode
   --  1=with fifo operation mode
   -------------------------------------------------
   -- internal signals
   -------------------------------------------------
   SIGNAL PCLK                     :  std_logic := '0';   
   SIGNAL PRESETN                  :  std_logic := '0';   
   SIGNAL UARTstatus1_data_out     :  std_logic_vector(7 DOWNTO 0);   
   SIGNAL UARTstatus2_data_out     :  std_logic_vector(7 DOWNTO 0);   
   SIGNAL UARTconfig1_bit8         :  std_logic;   
   SIGNAL UARTconfig1_parity_en    :  std_logic;   
   SIGNAL UARTconfig1_odd_n_even   :  std_logic;   
   SIGNAL UARTconfig2_bit8         :  std_logic;   
   SIGNAL UARTconfig2_parity_en    :  std_logic;   
   SIGNAL UARTconfig2_odd_n_even   :  std_logic;   
   SIGNAL PWDATA1                  :  std_logic_vector(7 DOWNTO 0);   
   SIGNAL PWDATA2                  :  std_logic_vector(7 DOWNTO 0);   
   SIGNAL txdata1                  :  std_logic;   
   SIGNAL rxdata1                  :  std_logic;   
   SIGNAL txdata2                  :  std_logic;   
   SIGNAL rxdata2                  :  std_logic;   
   SIGNAL PSEL1                    :  std_logic;   
   SIGNAL PSEL2                    :  std_logic;   
   SIGNAL count                    :  std_logic_vector(8 DOWNTO 0);   
   SIGNAL tdata                    :  xhdl_1;   
   SIGNAL rdata                    :  xhdl_1;   
   SIGNAL wdata                    :  std_logic_vector(7 DOWNTO 0);   
   SIGNAL wdata1                   :  std_logic_vector(7 DOWNTO 0);   
   SIGNAL wdata2                   :  std_logic_vector(7 DOWNTO 0);   
   SIGNAL rc                       :  std_logic_vector(8 DOWNTO 0);   
   SIGNAL tc                       :  std_logic_vector(8 DOWNTO 0);   
   SIGNAL i                        :  std_logic_vector(8 DOWNTO 0);   
   SIGNAL passflag                 :  std_logic_vector(8 DOWNTO 0);   
   SIGNAL par_err                  :  xhdl_1;   
   SIGNAL PWRITE1                  :  std_logic;   
   SIGNAL PWRITE2                  :  std_logic;   
   SIGNAL PENABLE1                 :  std_logic;   
   SIGNAL PENABLE2                 :  std_logic;   
   SIGNAL PADDR1                   :  std_logic_vector(8 DOWNTO 0);   
   SIGNAL PADDR2                   :  std_logic_vector(8 DOWNTO 0);   
   SIGNAL UARTstatus1_overflow     :  std_logic;   
   SIGNAL UARTstatus1_parity_err   :  std_logic;   
   SIGNAL UARTstatus1_rxrdy        :  std_logic;   
   SIGNAL UARTstatus1_txrdy        :  std_logic;   
   SIGNAL UARTstatus2_overflow     :  std_logic;   
   SIGNAL UARTstatus2_parity_err   :  std_logic;   
   SIGNAL UARTstatus2_rxrdy        :  std_logic;   
   SIGNAL UARTstatus2_txrdy        :  std_logic;   



BEGIN

   -------------------------------------------------
   -- 2 Meg baud selection based on 33 MHZ clock
   -------------------------------------------------
   -------------------------------------------------
   -- drive clock
   -------------------------------------------------
   
   PROCESS
   BEGIN
      WAIT FOR 15 * xhdl_timescale;
      
      PCLK <= NOT PCLK;    
   END PROCESS;
   
   -------------------------------------------------
   -- component instantiations
   -------------------------------------------------
   make_UART1 : CoreUARTapb 
      GENERIC MAP (
         PRG_PARITY => PRG_PARITY,
         TX_FIFO => TX_FIFO,
         BAUD_VALUE => BAUD_VALUE,
         FAMILY => FAMILY,
         RX_FIFO => RX_FIFO,
         PRG_BIT8 => PRG_BIT8,
         FIXEDMODE => FIXEDMODE)
      PORT MAP (
         PCLK => PCLK,
         PRESETN => PRESETN,
         PADDR => PADDR1(4 DOWNTO 2),
         PSEL => PSEL1,
         PENABLE => PENABLE1,
         PWRITE => PWRITE1,
         PWDATA => PWDATA1,
         PRDATA => UARTstatus1_data_out,
         TXRDY => UARTstatus1_txrdy,
         RXRDY => UARTstatus1_rxrdy,
         PARITY_ERR => UARTstatus1_parity_err,
         OVERFLOW => UARTstatus1_overflow,
         RX => rxdata1,
         TX => txdata1);   
   
   make_UART2 : CoreUARTapb 
      GENERIC MAP (
         PRG_PARITY => PRG_PARITY,
         TX_FIFO => TX_FIFO,
         BAUD_VALUE => BAUD_VALUE,
         FAMILY => FAMILY,
         RX_FIFO => RX_FIFO,
         PRG_BIT8 => PRG_BIT8,
         FIXEDMODE => FIXEDMODE)
      PORT MAP (
         PCLK => PCLK,
         PRESETN => PRESETN,
         PADDR => PADDR2(4 DOWNTO 2),
         PSEL => PSEL2,
         PENABLE => PENABLE2,
         PWRITE => PWRITE2,
         PWDATA => PWDATA2,
         PRDATA => UARTstatus2_data_out,
         TXRDY => UARTstatus2_txrdy,
         RXRDY => UARTstatus2_rxrdy,
         PARITY_ERR => UARTstatus2_parity_err,
         OVERFLOW => UARTstatus2_overflow,
         RX => rxdata2,
         TX => txdata2);   
   
   rxdata1 <= txdata2 ;
   rxdata2 <= txdata1 ;

   xhdl_7 : PROCESS

   VARIABLE xhdl_initial : BOOLEAN := TRUE;

   PROCEDURE cpu_write1 (
         address                 : IN std_logic_vector(8 DOWNTO 0);   
         data                    : IN std_logic_vector(7 DOWNTO 0))IS
   
      
   BEGIN
      WAIT UNTIL (PCLK'EVENT AND PCLK = '0');
      -- $display("CPU Write %04x = %04x",address,data);
      
      
      PWRITE1 <= '0';    
      WAIT UNTIL (PCLK'EVENT AND PCLK = '0');
      
      PENABLE1 <= '0';    
      PSEL1 <= '1';    
      PADDR1 <= address;    
      PWDATA1 <= data;    
      PWRITE1 <= '1';    
      WAIT UNTIL (PCLK'EVENT AND PCLK = '0');
      
      PENABLE1 <= '1';    
      WAIT UNTIL (PCLK'EVENT AND PCLK = '0');
      
      PWRITE1 <= '0';    
      PENABLE1 <= '0';    
      PSEL1 <= '0';    
   END PROCEDURE cpu_write1;


   PROCEDURE cpu_write2 (
         address                 : IN std_logic_vector(8 DOWNTO 0);   
         data                    : IN std_logic_vector(7 DOWNTO 0))IS
   
      
   BEGIN
      WAIT UNTIL (PCLK'EVENT AND PCLK = '0');
      -- $display("CPU Write %04x = %04x",address,data);
      
      
      PWRITE2 <= '0';    
      WAIT UNTIL (PCLK'EVENT AND PCLK = '0');
      
      PENABLE2 <= '0';    
      PSEL2 <= '1';    
      PADDR2 <= address;    
      PWDATA2 <= data;    
      PWRITE2 <= '1';    
      WAIT UNTIL (PCLK'EVENT AND PCLK = '0');
      
      PENABLE2 <= '1';    
      WAIT UNTIL (PCLK'EVENT AND PCLK = '0');
      
      PWRITE2 <= '0';    
      PENABLE2 <= '0';    
      PSEL2 <= '0';    
   END PROCEDURE cpu_write2;

   PROCEDURE cpu_read2 (
         address                 : IN std_logic_vector(8 DOWNTO 0))IS
   
      
   BEGIN
      WAIT UNTIL (PCLK'EVENT AND PCLK = '0');
      
      PWRITE2 <= '1';    
      WAIT UNTIL (PCLK'EVENT AND PCLK = '0');
      
      PENABLE2 <= '0';    
      PSEL2 <= '1';    
      PADDR2 <= address;    
      PWRITE2 <= '0';    
      WAIT UNTIL (PCLK'EVENT AND PCLK = '0');
      
      PENABLE2 <= '1';    
      WAIT UNTIL (PCLK'EVENT AND PCLK = '0');
      
      PWRITE2 <= '1';    
      PENABLE2 <= '0';    
      PSEL2 <= '0';    
      -- $display("CPU Read %04x = %04x",address, UARTstatus2_data_out);
      
      
   END PROCEDURE cpu_read2;

   -- This task does a cpu read
   PROCEDURE cpu_read1 (
         address                 : IN std_logic_vector(8 DOWNTO 0))IS
   
      
   BEGIN
      WAIT UNTIL (PCLK'EVENT AND PCLK = '0');