coreuartapb.vhd

Actel Fusion System Management Development Kit UART Example. Contains Libero design using CoreABC. P

-- Copyright 2007 Actel Corporation.  All rights reserved.
-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN 
-- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED 
-- IN ADVANCE IN WRITING.  
-- Rev: 3.1  12MAR07  HJ  : v3.1 CoreConsole Release  
library Ieee;
use iEEE.std_logIC_1164.all;
use IEee.STD_logic_ARIth.all;
use IEEE.std_LOGic_unSIGNEd.all;
entity cOREUartapb is
generic (FAMily: IntegeR := 15;
tx_fIFO: integER := 0;
RX_fifo: inTEGEr := 0;
baud_vALUE: inteGER := 0;
fiXEDMode: INteger := 0;
PRG_bit8: INTEger := 0;
prg_pARITY: inTEGER := 0); port (pCLK: in STD_logiC;
PResetn: in std_LOGic;
PADDR: in STD_logic_VECtor(4 downto 2);
Psel: in std_LOGIC;
PENable: in std_lOGIC;
pWRITe: in std_lOGIC;
pwdATA: in Std_logIC_Vector(7 downto 0);
Prdata: out std_LOGic_veCTOR(7 downto 0);
txrdY: out std_loGIC;
rxrdY: out std_LOGIC;
PARity_erR: out Std_loGIC;
OverflOW: out std_loGIC;
rx: in STd_logiC;
TX: out std_LOGIC);
end entity cOREUArtapb;

architecture traNSLAted of coreUARTapb is

component COreuart
generic (tx_FIFo: IntegeR;
RX_fifo: INTeger);
port (Reset_n: in STd_logiC;
Clk: in stD_LOgic;
wen: in stD_LOgic;
oen: in Std_LOGIC;
csn: in std_logIC;
DAta_in: in stD_logic_VECtor(7 downto 0);
rx: in Std_logic;
BAUd_val: in STD_logiC_Vector(7 downto 0);
BIT8: in std_lOGic;
PARIty_en: in std_LOGIc;
oDD_n_EVEn: in std_loGIC;
paritY_ERr: out stD_LOgic;
overflOW: out sTD_logic;
txrdY: out sTD_logic;
rxRDY: out std_lOGIC;
Data_ouT: out STd_logic_VECtor(7 downto 0);
tX: out stD_logic);
end component;

signal CUARTo1li: Std_loGIC_Vector(7 downto 0);

signal CUARTL1LI: Std_lOGIC_vectOR(2 downto 0);

signal CUARTi1li: std_lOGIC_veCTOR(7 downto 0);

signal CUARTooII: stD_logic_VECTor(7 downto 0);

signal CUARTlOII: std_LOGIC;

signal dATA_IN: Std_logiC_VEctor(7 downto 0);

signal daTA_Out: STD_logic_VECTOR(7 downto 0);

signal baud_vAL: STD_logic_VECTOR(7 downto 0);

signal Bit8: std_lOGIC;

signal PARIty_en: std_logiC;

signal odd_n_EVEN: STD_logic;

signal WEN: sTD_LOgic;

signal oen: Std_logiC;

signal csn: STD_Logic;

signal CUARTiOII: std_loGIC_Vector(1 downto 0);

signal CUARTOLII: STd_logic;

signal CUARTllii: STD_Logic;

signal CUARTiOOI: STD_logic_vECTOR(7 downto 0);

signal CUARToloi: stD_LOGic;

signal CUARTlloi: sTD_LOGic;

signal CUARTiloi: std_logiC;

signal CUARTILII: sTD_LOGic_vectOR(7 downto 0);

signal CUARTOIIi: std_logIC;

signal CUARTliiI: std_LOGIC;

signal CUARTiiiI: stD_LOGic;

signal CUARTo0II: std_LOGIC;

signal CUARTl0ii: std_loGIC;

function COnv_std_LOGic(VAL: in integeR)
return Std_logiC is
begin
if (val = 1) then
return ('1');
else
return ('0');
end if;
end CONv_std_loGIC;

begin
prdatA <= CUARTiLII;
txrdy <= CUARToIII;
RXRDY <= CUARTliII;
tx <= CUARTiiii;
parity_ERR <= CUARTo0iI;
OVERFlow <= CUARTL0ii;
WEN <= '0' when (PENable = '1' and PWrite = '1'
and padDR = "000") else
'1';
OEN <= '0' when (pENABLe = '1' and pwriTE = '0'
and PADDr = "001") else
'1';
cSN <= not PSEL;
DATA_in <= pwdata;
CUARTLOII <= (pSEL and not pwrite) and not penablE;
CUARTi0II:
process (PADDR,CUARTLoii,CUARTOOII,DATA_out,CUARTO1li,CUARTL1LI,CUARTl0II,CUARTo0II,CUARTliii,CUARToiii)
variable CUARTo1II: std_lOGIC_Vector(7 downto 0);
begin
if (CUARTloii = '1') then
case paddr(4 downto 2) is
when "000" =>
CUARTo1ii := "00000000";
when "001" =>
CUARTo1II := DATA_out;
when "010" =>
CUARTo1ii := CUARTO1li;
when "011" =>
CUARTo1ii := "00000"&CUARTl1LI;
when "100" =>
CUARTO1Ii := "0000"&CUARTl0II&CUARTO0II&CUARTliiI&CUARToiii;
when others =>
CUARTO1ii := CUARTOoii;
end case;
else
CUARTO1Ii := CUARTOOIi;
end if;
CUARTi1lI <= CUARTO1II;
end process CUARTI0II;
CUARTioii <= conv_STD_Logic_veCTOR(PRG_Parity,
2);
CUARTolii <= '1' when (CUARTIOII = "01" or CUARTIOii = "10") else
'0';
CUARTLLII <= '1' when (CUARTioii = "01") else
'0';
CUARTl1ii:
process (pcLK,presetN)
begin
if (not PResetn = '1') then
CUARTooii <= "00000000";
elsif (PCLK'event and Pclk = '1') then
CUARTooII <= CUARTi1li;
end if;
end process CUARTL1ii;
CUARTiLII <= CUARTOOII;
CUARTi1ii:
process (Pclk,presetn)
begin
if (not Presetn = '1') then
CUARTo1li <= "00000000";
elsif (Pclk'event and PCLk = '1') then
if (psel = '1' and Penable = '1'
and PwriTE = '1'
and PADDR(4 downto 2) = "010") then
CUARTO1Li <= pwdata;
else
CUARTo1li <= CUARTo1lI;
end if;
end if;
end process CUARTi1II;
CUARTIOOI <= COnv_std_LOGIC_vectoR(BAUD_value,
8) when FIXedmode /= 0 else
CUARTo1li;
BAud_val <= CUARTioOI;
CUARToo0i:
process (Pclk,presETN)
begin
if (not Presetn = '1') then
CUARTL1LI <= "000";
elsif (PCLk'EVENT and pcLK = '1') then
if (Psel = '1' and penABLE = '1'
and PWrite = '1'
and paddr(4 downto 2) = "011") then
CUARTl1LI <= PWdata(2 downto 0);
else
CUARTl1li <= CUARTL1LI;
end if;
end if;
end process CUARToo0i;
CUARToloi <= coNV_STd_logic(prg_bit8) when FIXEDMode /= 0 else
CUARTl1li(0);
bit8 <= CUARToloi;
CUARTLloi <= CUARTolii when fixedMODE /= 0 else
CUARTl1LI(1);
parITY_EN <= CUARTlloi;
CUARTiloi <= CUARTLLii when fixedmODE /= 0 else
CUARTL1li(2);
Odd_n_EVEN <= CUARTiloi;
CUARTlo0I: coREUARt
generic map (RX_fifo => RX_fifo,
TX_fifo => TX_Fifo)
port map (RESet_n => presETN,
Clk => Pclk,
wen => weN,
oeN => oen,
csn => Csn,
daTA_In => data_iN,
rx => Rx,
baud_VAL => Baud_vaL,
biT8 => bit8,
parITY_en => pARITy_en,
odd_N_Even => Odd_n_EVEN,
Parity_ERR => CUARTo0II,
oVERFlow => CUARTl0ii,
txrDY => CUARTOIII,
rxrdY => CUARTLIii,
data_OUT => daTA_OUt,
TX => CUARTIIIi);
end architecture TRANSlated;