fifo_256x8_fusion.vhd

Actel Fusion System Management Development Kit UART Example. Contains Libero design using CoreABC. P

library Ieee;
use ieEE.STD_lOGIC_1164.all;
library fUSION;
entity CUARTli is
port (Do: out STD_logiC_VECtor(7 downto 0);
Rclock: in STd_logic;
wCLOCK: in STd_logic;
Di: in STD_logic_veCTOR(7 downto 0);
wRB: in std_logIC;
RDB: in STd_logic;
RESet: in sTD_LOGic;
fulL: out STD_Logic;
empTY: out Std_logic);
end entity CUARTli;

architecture TranslaTED of CUARTli is

component CUARTII
port (data: in std_loGIC_vector(7 downto 0);
q: out STD_logic_vECTOR(7 downto 0);
WE: in stD_LOGIc;
re: in Std_logiC;
WCLOCK: in Std_logiC;
rCLOCK: in stD_LOGIc;
full: out stD_LOGIc;
eMPTY: out STD_LOgic;
reseT: in STD_logic;
AEMPTy: out stD_LOGIc;
afULL: out Std_logiC;
leveL: in std_logIC_VEctor(7 downto 0));
end component;

constant LEVEL: sTD_LOGic_vectOR(7 downto 0) := "11111111";

signal aeMPTY: sTD_LOgic;

signal afulL: std_loGIC;

signal CUARTo0: STD_logic_VECTOR(7 downto 0);

signal CUARTL0: std_loGIC_vector(7 downto 0);

signal CUARTi0: std_logIC;

signal CUARTO1: std_logIC;

signal CUARTl1: STd_logic;

signal CUARTI1: STD_Logic;

begin
Do <= CUARTL0;
FULL <= CUARTi0;
empty <= CUARTo1;
process (rclocK)
begin
if (RCLOCk'event and RCLock = '1') then
CUARTL0 <= CUARTo0;
end if;
end process;
CUARTool: CUARTii
port map (DATA => Di,
q => CUARTo0,
WE => WRB,
RE => RDB,
WCLOck => wclock,
RCLOck => rclock,
aemPTY => AEMpty,
Afull => CUARTi1,
FULL => CUARTi0,
Empty => CUARTo1,
reset => RESET,
Level => Level);
end architecture tranSLATED;

library ieee;
use IEEE.stD_LOGIc_1164.all;
library FUSIon;
entity CUARTii is
port (DAta: in STd_logic_VECTOr(7 downto 0);
q: out STd_logic_VECTOR(7 downto 0);
WE: in sTD_LOgic;
RE: in STD_Logic;
wcloCK: in std_LOGIc;
rclock: in std_logIC;
full: out std_logiC;
EMPTY: out STD_logic;
reset: in std_logIC;
AEmpty: out Std_logIC;
afuLL: out STD_logic;
leveL: in STD_logic_veCTOR(7 downto 0));
end entity CUARTiI;

architecture tranSLATED of CUARTii is

component inv
port (a: in std_LOGIC := 'U';
y: out std_lOGIC);
end component;

component FIFO4k18
port (aeval11,aevaL10,aeVAL9,AEVAL8,aevAL7,aeval6,AEVAL5,AEVAL4,aeval3,aeval2,aeval1,Aeval0,AFVal11,aFVAL10,aFVAL9,aFVAL8,AFVAL7,afval6,afval5,afval4,AFval3,AFVal2,Afval1,afval0,WD17,WD16,wd15,WD14,wd13,wD12,Wd11,wd10,wd9,WD8,WD7,wd6,WD5,wd4,WD3,wd2,WD1,wd0,ww0,ww1,wW2,Rw0,RW1,RW2,RPIPe,WEN,ren,WBlk,Rblk,wclk,RClk,RESEt,ESTOp,fSTOP: in STD_Logic := 'U';
RD17,rd16,rd15,rD14,RD13,rd12,rD11,RD10,Rd9,RD8,RD7,rD6,rD5,rd4,rD3,Rd2,rd1,RD0,full,AFULL,empty,AEMPTY: out STD_logic);
end component;

component vcc
port (y: out std_logIC);
end component;

component GNd
port (y: out std_lOGIC);
end component;

signal CUARTlol: sTD_LOGic;

signal CUARTiol: sTD_LOGic;

signal CUARTOll: Std_logiC;

signal CUARTLLL: std_logIC_VECtor(7 downto 0);

signal CUARTi0: stD_LOGic;

signal CUARTo1: std_loGIC;

signal CUARTIll: sTD_LOgic;

signal CUARToil: std_logIC;

begin
Q <= CUARTLLl;
FULL <= CUARTi0;
empTY <= CUARTO1;
aemPTY <= CUARTill;
afull <= CUARToil;
CUARTliL: VCC
port map (y => CUARTiol);
CUARTiil: gnD
port map (y => CUARToll);
CUARTo0l: inv
port map (a => re,
y => CUARTLOL);
fifobloCK0: fifo4K18
port map (AEval11 => CUARToll,
Aeval10 => CUARToLL,
AEVal9 => CUARToll,
AEVal8 => CUARToll,
AEval7 => CUARToll,
aeval6 => CUARTOLl,
aevAL5 => CUARTOll,
AEval4 => CUARToll,
aeval3 => CUARTiol,
AEVAL2 => CUARToll,
AEVal1 => CUARTOLL,
aevAL0 => CUARToll,
AFVAl11 => CUARTOll,
aFVAL10 => lEvel(7),
afval9 => leVEL(6),
AFval8 => LEVel(5),
afvaL7 => levEL(4),
AFVal6 => LEVEL(3),
afvAL5 => level(2),
Afval4 => LEvel(1),
aFVAL3 => leveL(0),
aFVAL2 => CUARToll,
afvaL1 => CUARTOLL,
afvaL0 => CUARTOll,
Wd17 => CUARToLL,
wd16 => CUARToLL,
wd15 => CUARToll,
Wd14 => CUARToll,
wd13 => CUARToll,
WD12 => CUARTOLl,
WD11 => CUARToll,
WD10 => CUARToll,
wd9 => CUARTOLl,
wd8 => CUARToll,
wd7 => data(7),
WD6 => data(6),
wd5 => daTA(5),
wd4 => dATA(4),
WD3 => DATA(3),
Wd2 => data(2),
Wd1 => dATA(1),
WD0 => DATa(0),
Ww0 => CUARTiol,
ww1 => CUARTiol,
ww2 => CUARToll,
RW0 => CUARTiol,
rw1 => CUARTIol,
RW2 => CUARTOLL,
rpipE => CUARToll,
Wen => we,
REN => CUARTlol,
wblk => CUARTOLL,
Rblk => CUARToLL,
Wclk => wclock,
rclk => Rclock,
reset => reseT,
EStop => CUARTiol,
fstop => CUARTiol,
RD17 => open ,
Rd16 => open ,
RD15 => open ,
rd14 => open ,
RD13 => open ,
RD12 => open ,
RD11 => open ,
rd10 => open ,
RD9 => open ,
RD8 => open ,
rd7 => CUARTLll(7),
rD6 => CUARTLll(6),
RD5 => CUARTlll(5),
RD4 => CUARTLLL(4),
Rd3 => CUARTlLL(3),
rd2 => CUARTllL(2),
rD1 => CUARTlll(1),
rD0 => CUARTlll(0),
FULL => open ,
afull => CUARTi0,
empTY => CUARTo1,
AEMPty => CUARTILl);
end architecture transLATED;