clock_gen.vhd

Actel Fusion System Management Development Kit UART Example. Contains Libero design using CoreABC. P

-- Copyright 2007 Actel Corporation.  All rights reserved.
-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN 
-- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED 
-- IN ADVANCE IN WRITING.  
-- Rev: 3.0  21FEB07  HJ  : v3.0 CoreConsole Release  
library Ieee;
use IEEE.STD_lOGIC_1164.all;
use ieEE.stD_LOGIc_arith.all;
use iEEE.sTD_LOgic_unsiGNEd.all;
entity CLock_gen is
port (clk: in std_LOGIC;
rESET_N: in Std_logiC;
Baud_val: in STD_logic_VECTOr(7 downto 0);
BAUD_clock: out STD_logic;
xmit_PULSE: out std_logIC);
end clock_geN;

architecture CUARTo of Clock_geN is

signal CUARTl: STD_logic_VECTOR(7 downto 0);

signal CUARTI: std_logIC;

signal CUARTOL: STd_logic;

signal CUARTll: Std_logiC_VECTor(3 downto 0);

begin
CUARTil:
process (clk,reseT_N)
begin
if (reseT_N = '0') then
CUARTl <= "00000000";
CUARTi <= '0';
elsif (CLK'eVENT and clk = '1') then
if (CUARTl = "00000000") then
CUARTL <= BAud_val;
CUARTi <= '1';
else
CUARTL <= CUARTL-'1';
CUARTi <= '0';
end if;
end if;
end process;
CUARTOI:
process (clk,REset_n)
begin
if (reset_N = '0') then
CUARTLL <= "0000";
CUARTol <= '0';
elsif (CLK'event and CLK = '1') then
if (CUARTi = '1') then
CUARTLl <= CUARTll+'1';
if (CUARTll = "1111") then
CUARTOL <= '1';
else
CUARTOL <= '0';
end if;
end if;
end if;
end process;
XMit_pulse <= CUARTOL and CUARTI;
Baud_clocK <= CUARTI;
end CUARTo;