coreuart.vhd

Actel Fusion System Management Development Kit UART Example. Contains Libero design using CoreABC. P

-- Copyright 2007 Actel Corporation.  All rights reserved.
-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN 
-- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED 
-- IN ADVANCE IN WRITING.  
-- Rev: 3.0  21FEB07  HJ  : v3.0 CoreConsole Release  
library Ieee;
use ieee.STD_lOGIC_1164.all;
use ieee.Std_logiC_ARITh.all;
use IEEE.STD_Logic_unSIGNEd.all;
entity coreUART is
generic (FAMILy: integER := 15;
tx_fIFO: integeR := 0;
Rx_fifO: Integer := 0); port (reseT_n: in std_loGIC;
clk: in std_lOGIC;
Wen: in std_LOGic;
oen: in STd_logiC;
csn: in STD_logic;
daTA_In: in STd_logiC_VECtor(7 downto 0);
RX: in std_LOGic;
Baud_vaL: in std_lOGIC_vectOR(7 downto 0);
BIT8: in STD_logic;
Parity_EN: in std_LOGIc;
odd_N_Even: in STD_logic;
pARITy_err: out STd_logiC;
OVERflow: out sTD_logic;
tXRDY: out STD_logic;
Rxrdy: out stD_LOgic;
DATa_out: out std_lOGIC_vectOR(7 downto 0);
TX: out sTD_Logic);
end entity cOREUArt;

architecture TranslaTED of COReuart is

component rx_aSYNC
generic (Rx_fifo: iNTEger := 0);
port (clk: in Std_lOGIC;
baUD_clock: in STD_logic;
reset_N: in sTd_logic;
bIT8: in stD_LOGic;
PArity_eN: in std_LOGIC;
ODD_n_evEN: in Std_lOGIC;
Read_rX_BYTe: in stD_LOGic;
CLEar_parITY: in std_loGIC;
rx: in std_LOGIC;
OVERflow: out STD_logiC;
PARITy_err: out STD_logic;
CLEar_parITY_en: out std_LOGIC;
receivE_FUll: out STD_logic;
rx_bYTE: out STd_logiC_Vector(7 downto 0);
FIFO_write: out stD_LOgic);
end component;

component TX_async
generic (Tx_fifo: integER := 0);
port (CLK: in std_LOGIC;
xmiT_pulse: in stD_LOgic;
RESEt_n: in std_loGIC;
RST_tx_eMPTY: in STD_logic;
Tx_holD_REg: in STD_logic_VECtor(7 downto 0);
Tx_dout_REG: in std_logIC_Vector(7 downto 0);
fifO_emptY: in STD_logiC;
fifo_FUll: in stD_logic;
bit8: in STd_logiC;
pariTY_en: in STd_logiC;
odd_N_EVen: in STD_logiC;
txRDY: out STD_logIC;
Tx: out STD_logic;
fifO_read_tX: out STd_logIC);
end component;

component CLOck_gen
port (CLK: in std_lOGIC;
RESet_n: in std_logic;
baud_VAl: in sTD_logiC_VECtor(7 downto 0);
bAUD_clOCK: out Std_loGIC;
xmit_pulse: out std_lOGIC);
end component;

component CUARTlI is
port (Do: out stD_Logic_vECTOR(7 downto 0);
rcLOCK: in std_LOGIC;
WCLock: in STD_logic;
di: in sTD_loGIC_Vector(7 downto 0);
wRB: in std_LOGIC;
Rdb: in std_LOGic;
Reset: in Std_logiC;
FULL: out Std_logic;
EMPty: out std_LOGIC);
end component;

constant CUARTl00l: std_loGIC_Vector(1 downto 0) := "00";

constant CUARTi00L: sTD_LOGic_vectOR(1 downto 0) := "01";

constant CUARTo10l: STD_LOgic_vecTOR(1 downto 0) := "10";

constant CUARTl10L: std_LOGIC_vector(1 downto 0) := "11";

signal CUARTi10L: stD_LOGIc;

signal CUARTOO1l: std_logIC;

signal CUARTlo1l: std_logIC;

signal FIFO_write: std_LOGIC;

signal XMIt_pulse: STD_LOgic;

signal bauD_CLOCk: std_loGIC;

signal rst_tx_eMPTY: std_logIC;

signal tx_hold_REG: STD_LOgic_vecTOR(7 downto 0);

signal tx_DOUT_Reg: STD_Logic_veCTOR(7 downto 0);

signal CUARTiO1L: STD_logic_vECTOR(7 downto 0);

signal REAd_rx_byTE: STD_logic;

signal CUARTOl1l: std_LOGIC_vector(7 downto 0);

signal Rx_byte: Std_logiC_VECTor(7 downto 0);

signal CUARTll1l: std_LOGIC_vector(7 downto 0);

signal CUARTIL1l: std_LOGIC;

signal CUARToi1L: STD_logic;

signal CUARTLi1l: std_LOGIC;

signal CUARTiI1L: STD_logic;

signal fifo_READ_tx: std_loGIC;

signal CUARTo01L: STD_logic;

signal CUARTl01L: STD_LOgic;

signal CLear_pariTY: STD_logic;

signal CLEAR_parity_EN: STD_logic;

signal CUARTI01L: Std_logic;

signal CUARTo11L: STD_Logic;

signal CUARTL11l: std_lOGIC;

signal CUARTi11l: std_LOGIC;

signal CUARToooi: STD_logic;

signal CUARTlooi: stD_LOGic;

signal CUARTlo0: std_LOGIc;

signal CUARTiooi: STD_Logic;

signal CUARToLOI: sTD_LOgic;

signal CUARTlloI: STD_logic;

signal CUARTILOI: sTD_LOgic;

signal CUARToioi: std_logIC_VECtor(7 downto 0);

signal CUARTlioi: std_lOGIC;

signal CUARTIIOI: std_logIC;

signal CUARTo0OI: std_LOGIC;

signal CUARTl0OI: std_LOGIC;

signal CUARTi0oI: std_lOGIC;

signal CUARTo1oI: std_lOGIC;

signal CUARTL1OI: STD_Logic_vecTOR(7 downto 0);

signal CUARTI1oi: STD_logic;

signal CUARToOLI: STD_Logic;

signal CUARToLOL: std_logIC_VEctor(1 downto 0);

signal CUARTloli: std_logIC_VEctor(1 downto 0);

begin
Parity_eRR <= CUARTo0oi;
OVERflow <= CUARTL0OI;
txrDY <= CUARTI0oi;
RXRDY <= CUARTo1oi;
DATa_out <= CUARTL1oi;
tx <= CUARTI1OI;
CUARTIOLI:
process (CLK,RESEt_n)
begin
if (REset_n = '0') then
TX_hold_reG <= '0'&'0'&'0'&'0'&'0'&'0'&'0'&'0';
CUARTii1L <= '1';
elsif (CLK'eveNT and CLK = '1') then
CUARTii1l <= '1';
if (csN = '0' and WEN = '0') then
Tx_hold_REG <= dATA_IN;
CUARTII1L <= '0';
end if;
end if;
end process CUARTIoli;
CUARTLO0 <= '1' when (wen = '0' and csn = '0') else
'0';
rst_TX_Empty <= CUARTlo0;
process (Rx_byte,CUARTol1L,CUARTO0OI)
variable CUARTOLLi: std_lOGIC_Vector(7 downto 0);
begin
if (RX_fifo = 2#0#) then
CUARTolli := RX_BYTe;
else
if (CUARTo0OI = '1') then
CUARTolLI := Rx_byte;
else
CUARTOLLi := CUARTol1l;
end if;
end if;
CUARTl1OI <= CUARTolli;
end process;
CUARTioOI <= '1' when (Csn = '0' and OEN = '0') else
'0';
CUARTolOI <= (CUARTiooI) when (RX_fifo = 2#0#) else
not CUARTL01l;
Read_rx_BYTE <= CUARTolOI;
CUARTlLOI <= '1' when (CSn = '0' and oen = '0') else
'0';
CUARTILOi <= CUARTO11l when RX_fifo /= 0 else
(CUARTLLOi);
CLEar_parITY <= CUARTILOI;
CUARTOIOi <= RX_Byte when (CUARTo0OI = '0') else
"00000000";
CUARTll1L <= CUARTOIOi;
process (CUARToO1L,CUARTOOli)
variable CUARTLLli: sTD_Logic;
begin
if (Rx_fifO = 2#0#) then
CUARTllli := CUARToo1L;
else
CUARTllli := not CUARToOLI;
end if;
CUARTo1oi <= CUARTLLLI;
end process;
process (CLK,reset_N)
begin
if (rESET_n = '0') then
CUARTo11L <= '0';
elsif (CLK'evENT and clK = '1') then
CUARTi01l <= CLEAr_pariTY_En;
CUARTO11l <= CUARTI01l;
end if;
end process;
process (clk,reseT_N)
begin
if (resET_N = '0') then
CUARTolol <= CUARTL00l;
elsif (CLk'eVENT and Clk = '1') then
CUARTOLOL <= CUARTloli;
end if;
end process;
process (CUARTolOL,CUARTooli,CUARTOI1L)
begin
CUARTLOli <= CUARTOlol;
CUARTli1l <= '1';
CUARToooi <= '0';
case CUARTOLOL is
when CUARTl00L =>
if (CUARTooli = '1' and CUARToi1l = '0') then
CUARTLOli <= CUARTI00l;
CUARTLI1L <= '0';
end if;
when CUARTi00L =>
CUARTLOLI <= CUARTo10L;
when CUARTO10L =>
CUARTloli <= CUARTl10L;
when CUARTL10l =>
CUARTloli <= CUARTl00l;
CUARTOOoi <= '1';
when others =>
CUARTloLI <= CUARTolol;
end case;
end process;
process (Clk,Reset_N)
begin
if (reseT_n = '0') then
CUARToL1L <= "00000000";
elsif (Clk'EVENt and Clk = '1') then
if (CUARTOooi = '1') then
CUARTol1l <= CUARTIO1l;
end if;
end if;
end process;
process (cLK,reSET_N)
begin
if (reset_n = '0') then
CUARToOLI <= '1';
elsif (clk'EVEnt and clk = '1') then
if (CUARTOOOI = '1') then
CUARToolI <= '0';
else
if (csn = '0' and OEN = '0') then
CUARTOOLI <= '1';
end if;
end if;
end if;
end process;
CUARTlioI <= CUARTl01l when rx_fifO /= 0 else
CUARTI10L;
CUARTl0oI <= CUARTlioI;
CUARTiioi <= '1' when (CUARTo0oi = '1') else
fifo_wrITE;
CUARTlo1L <= CUARTiioI;
CUARTilli: Clock_geN
port map (CLK => CLK,
resET_N => reset_n,
BAud_val => baUD_VAL,
baud_CLOCk => BAUD_clock,
xMIT_PUlse => XMIT_pulse);
CUARTOili: tx_ASYNC
generic map (tx_fifo => TX_fifo)
port map (clk => CLk,
xmiT_PULSe => xMit_pULSE,
RESET_n => reSET_N,
RST_Tx_empty => rst_TX_EMpty,
tx_holD_REG => TX_HOLd_reg,
Tx_dout_REG => tx_doUT_REg,
fiFO_EMPTy => CUARTIL1L,
FIFO_full => CUARTo01l,
BIT8 => Bit8,
PARIty_en => Parity_en,
odd_n_EVEN => odd_n_EVEN,
txrdY => CUARTi0oi,
Tx => CUARTi1OI,
Fifo_reaD_TX => fifO_READ_tx);
CUARTLILI: RX_Async
generic map (RX_Fifo => rx_fiFO)
port map (CLK => CLK,
bauD_CLOCk => baud_clOCK,
Reset_n => reset_N,
BIT8 => BIT8,
PARITy_en => Parity_en,
odd_n_EVEN => odd_n_EVEN,
READ_rx_bytE => Read_rx_BYTE,
CLEAR_parity => Clear_paRITY,
RX => rX,
OVERFLOw => CUARTi10l,
paRITY_Err => CUARTo0oi,
clear_PARITY_en => cleAR_PARIty_en,
RECeive_fulL => CUARTOO1l,
Rx_byte => RX_byte,
fifo_wrITE => Fifo_wriTE);
CUARTiili:
if (tx_fifO = 2#1#)
generate
CUARTo0LI: CUARTLI
port map (do => tx_dout_REG,
RCLock => clk,
WCLOck => clk,
DI => Data_in,
WRB => CUARTII1L,
rdb => fiFO_REAd_tx,
reSET => reset_N,
Full => CUARTo01L,
empty => CUARTIl1l);
end generate;
CUARTl0li:
if (rX_FIFo = 2#1#)
generate
CUARTi0LI: CUARTLI
port map (DO => CUARTio1L,
rCLOCK => CLK,
WClock => CLk,
DI => CUARTll1L,
WRB => CUARTlo1L,
RDb => CUARTli1L,
resET => resET_N,
fuLL => CUARTL01l,
EMPTy => CUARTOI1l);
end generate;
end architecture TRANslated;