📄 tb_user_corepwm.vhd
字号:
end component;
TYPE xhdl_1 IS ARRAY (0 TO 11) OF std_logic_vector(8 * 79 DOWNTO 1);
constant PERIOD_DATA : INTEGER := 2 ** APB_DWIDTH - 3;
constant ENABLE_DATA : INTEGER := 2 ** PWM_NUM - 1;
constant TIMEOUT : INTEGER := 3 * (2 ** APB_DWIDTH) ;
constant dash_str :string(1 to 77) :=
"-----------------------------------------------------------------------------";
constant uline_str :string(1 to 77) :=
"_____________________________________________________________________________";
constant pound_str :string(1 to 77) :=
"#############################################################################";
constant space77_str :string(1 to 77) :=
" ";
constant copyright_str :string(1 to 77) :=
"(c) Copyright 2008 Actel Corporation. All rights reserved. ";
constant tb_name_str :string(1 to 77) :=
"Testbench for: CorePWM ";
constant tb_ver_str :string(1 to 77) :=
"Version: 3.0.100 May 6th, 2008 ";
constant lsb_str :string(1 to 3) := "LSB";
constant msb_str :string(1 to 3) := "MSB";
type STR_ARRAY1 is array (integer range 0 to 11) of string (1 to 77);
-- initialization of testbench string
constant init_str_mem :STR_ARRAY1 := (
space77_str,space77_str,uline_str,space77_str,copyright_str,space77_str,
tb_name_str,tb_ver_str,uline_str,space77_str,space77_str,space77_str
);
-- Run simulation for given number of clock cycles
procedure cyc(
constant c: in integer range 0 to 65536) is
begin
cloop: for i in 1 to c loop
wait for SYS_CLK_CYCLE * 1 ns ;
end loop cloop;
end cyc;
SIGNAL PCLK : std_logic;
SIGNAL PRESETN : std_logic;
SIGNAL PSEL : std_logic;
SIGNAL PENABLE : std_logic;
SIGNAL PWRITE : std_logic;
SIGNAL PADDR : std_logic_vector(7 DOWNTO 0);
SIGNAL PWDATA : std_logic_vector(APB_DWIDTH-1 DOWNTO 0);
SIGNAL PRDATA : std_logic_vector(APB_DWIDTH-1 DOWNTO 0);
SIGNAL PWM : std_logic_vector(PWM_NUM DOWNTO 1);
SIGNAL simerrors : integer;
SIGNAL count_high : integer;
SIGNAL count_low : integer;
SIGNAL real_error : integer;
SIGNAL sum : std_logic_vector(7 DOWNTO 0);
SIGNAL pwm_diff : std_logic;
SIGNAL stopsim :boolean;
SIGNAL my_scale_tmp : unsigned (7 downto 0);
BEGIN
-- generate the system clock
PCLK_proc: process
begin
if (stopsim) then
wait; -- end simulation
else
PCLK <= '0';
wait for ((SYS_CLK_CYCLE * 1 ns)/2);
PCLK <= '1';
wait for ((SYS_CLK_CYCLE * 1 ns)/2);
end if;
end process;
corepwm_xhdl12 : corepwm
GENERIC MAP(
FAMILY => FAMILY ,
PWM_NUM => PWM_NUM ,
APB_DWIDTH => APB_DWIDTH ,
FIXED_PRESCALE_EN => FIXED_PRESCALE_EN ,
FIXED_PRESCALE => FIXED_PRESCALE ,
FIXED_PERIOD_EN => FIXED_PERIOD_EN ,
FIXED_PERIOD => FIXED_PERIOD ,
DAC_MODE1 => DAC_MODE1 ,
DAC_MODE2 => DAC_MODE2 ,
DAC_MODE3 => DAC_MODE3 ,
DAC_MODE4 => DAC_MODE4 ,
DAC_MODE5 => DAC_MODE5 ,
DAC_MODE6 => DAC_MODE6 ,
DAC_MODE7 => DAC_MODE7 ,
DAC_MODE8 => DAC_MODE8 ,
DAC_MODE9 => DAC_MODE9 ,
DAC_MODE10 => DAC_MODE10 ,
DAC_MODE11 => DAC_MODE11 ,
DAC_MODE12 => DAC_MODE12 ,
DAC_MODE13 => DAC_MODE13 ,
DAC_MODE14 => DAC_MODE14 ,
DAC_MODE15 => DAC_MODE15 ,
DAC_MODE16 => DAC_MODE16 ,
SHADOW_REG_EN1 => SHADOW_REG_EN1 ,
SHADOW_REG_EN2 => SHADOW_REG_EN2 ,
SHADOW_REG_EN3 => SHADOW_REG_EN3 ,
SHADOW_REG_EN4 => SHADOW_REG_EN4 ,
SHADOW_REG_EN5 => SHADOW_REG_EN5 ,
SHADOW_REG_EN6 => SHADOW_REG_EN6 ,
SHADOW_REG_EN7 => SHADOW_REG_EN7 ,
SHADOW_REG_EN8 => SHADOW_REG_EN8 ,
SHADOW_REG_EN9 => SHADOW_REG_EN9 ,
SHADOW_REG_EN10 => SHADOW_REG_EN10 ,
SHADOW_REG_EN11 => SHADOW_REG_EN11 ,
SHADOW_REG_EN12 => SHADOW_REG_EN12 ,
SHADOW_REG_EN13 => SHADOW_REG_EN13 ,
SHADOW_REG_EN14 => SHADOW_REG_EN14 ,
SHADOW_REG_EN15 => SHADOW_REG_EN15 ,
SHADOW_REG_EN16 => SHADOW_REG_EN16 ,
FIXED_PWM_POS_EN1 => FIXED_PWM_POS_EN1 ,
FIXED_PWM_POS_EN2 => FIXED_PWM_POS_EN2 ,
FIXED_PWM_POS_EN3 => FIXED_PWM_POS_EN3 ,
FIXED_PWM_POS_EN4 => FIXED_PWM_POS_EN4 ,
FIXED_PWM_POS_EN5 => FIXED_PWM_POS_EN5 ,
FIXED_PWM_POS_EN6 => FIXED_PWM_POS_EN6 ,
FIXED_PWM_POS_EN7 => FIXED_PWM_POS_EN7 ,
FIXED_PWM_POS_EN8 => FIXED_PWM_POS_EN8 ,
FIXED_PWM_POS_EN9 => FIXED_PWM_POS_EN9 ,
FIXED_PWM_POS_EN10 => FIXED_PWM_POS_EN10 ,
FIXED_PWM_POS_EN11 => FIXED_PWM_POS_EN11 ,
FIXED_PWM_POS_EN12 => FIXED_PWM_POS_EN12 ,
FIXED_PWM_POS_EN13 => FIXED_PWM_POS_EN13 ,
FIXED_PWM_POS_EN14 => FIXED_PWM_POS_EN14 ,
FIXED_PWM_POS_EN15 => FIXED_PWM_POS_EN15 ,
FIXED_PWM_POS_EN16 => FIXED_PWM_POS_EN16 ,
FIXED_PWM_POSEDGE1 => FIXED_PWM_POSEDGE1 ,
FIXED_PWM_POSEDGE2 => FIXED_PWM_POSEDGE2 ,
FIXED_PWM_POSEDGE3 => FIXED_PWM_POSEDGE3 ,
FIXED_PWM_POSEDGE4 => FIXED_PWM_POSEDGE4 ,
FIXED_PWM_POSEDGE5 => FIXED_PWM_POSEDGE5 ,
FIXED_PWM_POSEDGE6 => FIXED_PWM_POSEDGE6 ,
FIXED_PWM_POSEDGE7 => FIXED_PWM_POSEDGE7 ,
FIXED_PWM_POSEDGE8 => FIXED_PWM_POSEDGE8 ,
FIXED_PWM_POSEDGE9 => FIXED_PWM_POSEDGE9 ,
FIXED_PWM_POSEDGE10 => FIXED_PWM_POSEDGE10,
FIXED_PWM_POSEDGE11 => FIXED_PWM_POSEDGE11,
FIXED_PWM_POSEDGE12 => FIXED_PWM_POSEDGE12,
FIXED_PWM_POSEDGE13 => FIXED_PWM_POSEDGE13,
FIXED_PWM_POSEDGE14 => FIXED_PWM_POSEDGE14,
FIXED_PWM_POSEDGE15 => FIXED_PWM_POSEDGE15,
FIXED_PWM_POSEDGE16 => FIXED_PWM_POSEDGE16,
FIXED_PWM_NEG_EN1 => FIXED_PWM_NEG_EN1 ,
FIXED_PWM_NEG_EN2 => FIXED_PWM_NEG_EN2 ,
FIXED_PWM_NEG_EN3 => FIXED_PWM_NEG_EN3 ,
FIXED_PWM_NEG_EN4 => FIXED_PWM_NEG_EN4 ,
FIXED_PWM_NEG_EN5 => FIXED_PWM_NEG_EN5 ,
FIXED_PWM_NEG_EN6 => FIXED_PWM_NEG_EN6 ,
FIXED_PWM_NEG_EN7 => FIXED_PWM_NEG_EN7 ,
FIXED_PWM_NEG_EN8 => FIXED_PWM_NEG_EN8 ,
FIXED_PWM_NEG_EN9 => FIXED_PWM_NEG_EN9 ,
FIXED_PWM_NEG_EN10 => FIXED_PWM_NEG_EN10 ,
FIXED_PWM_NEG_EN11 => FIXED_PWM_NEG_EN11 ,
FIXED_PWM_NEG_EN12 => FIXED_PWM_NEG_EN12 ,
FIXED_PWM_NEG_EN13 => FIXED_PWM_NEG_EN13 ,
FIXED_PWM_NEG_EN14 => FIXED_PWM_NEG_EN14 ,
FIXED_PWM_NEG_EN15 => FIXED_PWM_NEG_EN15 ,
FIXED_PWM_NEG_EN16 => FIXED_PWM_NEG_EN16 ,
FIXED_PWM_NEGEDGE1 => FIXED_PWM_NEGEDGE1 ,
FIXED_PWM_NEGEDGE2 => FIXED_PWM_NEGEDGE2 ,
FIXED_PWM_NEGEDGE3 => FIXED_PWM_NEGEDGE3 ,
FIXED_PWM_NEGEDGE4 => FIXED_PWM_NEGEDGE4 ,
FIXED_PWM_NEGEDGE5 => FIXED_PWM_NEGEDGE5 ,
FIXED_PWM_NEGEDGE6 => FIXED_PWM_NEGEDGE6 ,
FIXED_PWM_NEGEDGE7 => FIXED_PWM_NEGEDGE7 ,
FIXED_PWM_NEGEDGE8 => FIXED_PWM_NEGEDGE8 ,
FIXED_PWM_NEGEDGE9 => FIXED_PWM_NEGEDGE9 ,
FIXED_PWM_NEGEDGE10 => FIXED_PWM_NEGEDGE10,
FIXED_PWM_NEGEDGE11 => FIXED_PWM_NEGEDGE11,
FIXED_PWM_NEGEDGE12 => FIXED_PWM_NEGEDGE12,
FIXED_PWM_NEGEDGE13 => FIXED_PWM_NEGEDGE13,
FIXED_PWM_NEGEDGE14 => FIXED_PWM_NEGEDGE14,
FIXED_PWM_NEGEDGE15 => FIXED_PWM_NEGEDGE15,
FIXED_PWM_NEGEDGE16 => FIXED_PWM_NEGEDGE16
)
PORT MAP(
PRESETN => PRESETN,
PCLK => PCLK ,
PSEL => PSEL ,
PENABLE => PENABLE,
PWRITE => PWRITE ,
PADDR => PADDR ,
PWDATA => PWDATA ,
PRDATA => PRDATA ,
PWM => PWM
);
testing : PROCESS
VARIABLE i2 : integer;
VARIABLE i : integer;
VARIABLE j : integer;
VARIABLE k : integer;
VARIABLE l : integer;
VARIABLE t : integer;
VARIABLE lmsb_str : std_logic_vector(8 * 79 DOWNTO 1);
VARIABLE dtmp : std_logic_vector(7 DOWNTO 0);
VARIABLE fixed_enable_var : std_logic_vector(7 DOWNTO 0);
VARIABLE fixed_int_mask_var : std_logic_vector(7 DOWNTO 0);
variable simerrorsv : natural range 0 to 2047;
variable sum_count : natural range 0 to 2047;
variable scale_tmp : unsigned (7 downto 0);
BEGIN
i := 0;
j := 0;
k := 0;
l := 0;
t := 0;
dtmp := "00000000";
fixed_enable_var := "00000000";
fixed_int_mask_var := "00000000";
simerrors <= simerrorsv;
simerrorsv := 0;
sum <= "00000000";
sum_count := 0;
pwm_diff <= '0';
count_high <= 0;
count_low <= 0;
real_error <= 0;
scale_tmp := "00000000";
my_scale_tmp <= "00000000";
i := 0;
WHILE (i < 12) LOOP
printf( init_str_mem(i));
i := i + 1;
END LOOP;
PRESETN <= '0';
PSEL <= '0';
PWDATA <= (others => '0');
PADDR <= (others => '0');
PWRITE <= '0';
PENABLE <= '0';
WAIT UNTIL (PCLK'EVENT AND PCLK = '1');
PRESETN <= '1';
printf("PWM outputs set to %0d", fmt(PWM_NUM));
printf("\nCorePWM tests beginning:\n\n");
printf("Writing all Registers\n");
i := 0;
WHILE (i < PWM16_NEGEDGE_ADR) LOOP
cpu_wr(to_bitvector(std_logic_vector(to_unsigned(i, 8))),to_bitvector(std_logic_vector(to_unsigned(i, 8))),PCLK, PADDR, PWDATA, PSEL,PWRITE,PENABLE);
i := i + 4;
END LOOP;
printf("Reading all Registers\n");
i := 0;
WHILE (i < PWM16_NEGEDGE_ADR) LOOP
IF (i = PWM4_POSEDGE_ADR AND FIXED_PWM_POS_EN4 = 0) THEN
cpu_rd(to_bitvector(std_logic_vector(to_unsigned(i, 8))), to_bitvector(std_logic_vector(to_unsigned(i, 8))),PCLK, PADDR, PRDATA, PSEL,PWRITE,PENABLE,simerrorsv);
simerrors <= simerrorsv;
ELSE
cpu_rd(to_bitvector(std_logic_vector(to_unsigned(i, 8))), to_bitvector(std_logic_vector(to_unsigned(i, 8))),PCLK, PADDR, PRDATA, PSEL,PWRITE,PENABLE,simerrorsv);
simerrors <= simerrorsv;
END IF;
i := i + 4;
END LOOP;
printf("Configuring Channels\n");
cpu_wr(to_bitvector(std_logic_vector(to_unsigned(PRESCALE_ADR, 8))),to_bitvector(std_logic_vector(to_unsigned(1, 8))),PCLK, PADDR, PWDATA, PSEL,PWRITE,PENABLE);
cpu_wr(to_bitvector(std_logic_vector(to_unsigned(PERIOD_ADR, 8))),to_bitvector(std_logic_vector(to_unsigned(PERIOD_DATA, 8))),PCLK, PADDR, PWDATA, PSEL,PWRITE,PENABLE);
cpu_wr(to_bitvector(std_logic_vector(to_unsigned(ENABLE1_ADR, 8))),to_bitvector(std_logic_vector(to_unsigned(255, 8))),PCLK, PADDR, PWDATA, PSEL,PWRITE,PENABLE);
cpu_wr(to_bitvector(std_logic_vector(to_unsigned(ENABLE2_ADR, 8))),to_bitvector(std_logic_vector(to_unsigned(255, 8))),PCLK, PADDR, PWDATA, PSEL,PWRITE,PENABLE);
iloop: for i in 1 to PWM_NUM loop
printf("Waiting for PWM%0d Output to Change....", fmt(i));
tloop: for t in 1 to TIMEOUT loop
wait for SYS_CLK_CYCLE * 1 ns ;
IF (PWM(i) = '1') THEN
printf("....................Change Detected...\n");
exit tloop;
END IF;
IF (t = TIMEOUT) THEN
printf("*** Error: Timed Out Waiting For Change \n");
simerrorsv := simerrorsv + 1;
simerrors <= simerrorsv;
END IF;
END LOOP tloop;
END LOOP iloop;
printf(" ");
printf("All tests for PWM = %0d complete with:", fmt(PWM_NUM));
printf("%0d Errors.", fmt(simerrors));
printf(" ");
ASSERT (FALSE) REPORT "ending simulation" SEVERITY WARNING;
stopsim <= true;
wait;
END PROCESS;
END translated;⌨️ 快捷键说明
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