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📁 Actel Fusion System Management Development Kit UART Example. Contains Libero design using CoreABC. P
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123 
generate
process (paddr,pwm_posEDGE_OUT_wire,Pwm_negedge_OUT_WIre)
begin
case (paDDR) is
when "000100" =>
CPWMl0l <= PWM_POSedge_out_wIRE(1*apb_dwiDTH downto 0*aPB_DWIDTH+1);
when "000101" =>
CPWMl0l <= pwm_negeDGE_OUT_wire(1*apb_dWIDTH downto 0*APB_DWIdth+1);
when "000110" =>
CPWML0L <= pwm_pOSEDGE_out_wire(2*Apb_dwidth downto 1*APb_dwidth+1);
when "000111" =>
CPWML0L <= pwm_nEGEDGE_out_wire(2*APB_DWidth downto 1*apB_DWIDTH+1);
when "001000" =>
CPWML0L <= PWM_Posedge_out_WIRE(3*Apb_dwidth downto 2*APB_dwidth+1);
when "001001" =>
CPWMl0l <= PWM_NEgedge_out_wIRE(3*APB_dwidth downto 2*APB_DWIdth+1);
when "001010" =>
CPWMl0l <= pWM_POSEdge_out_wIRE(4*APb_dwidth downto 3*APB_DWIDth+1);
when "001011" =>
CPWMl0l <= pwm_neGEDGE_Out_wire(4*aPB_DWIDTH downto 3*APB_DWidth+1);
when "001100" =>
CPWMl0l <= pwm_posEDGE_OUt_wire(5*apb_dwiDTH downto 4*APB_dwidth+1);
when "001101" =>
CPWML0l <= PWM_negedge_oUT_WIRE(5*Apb_dwidth downto 4*APB_Dwidth+1);
when "001110" =>
CPWMl0l <= PWM_POsedge_out_wIRE(6*aPB_DWIDTH downto 5*apb_dwidtH+1);
when "001111" =>
CPWMl0l <= pWM_NEGEdge_out_wIRE(6*apb_dwidth downto 5*apb_DWIDTH+1);
when "010000" =>
CPWML0L <= PWM_posedge_out_WIRE(7*apb_DWIDTH downto 6*apb_dWIDTH+1);
when "010001" =>
CPWMl0l <= pwm_nEGEDGE_Out_wire(7*Apb_dwidth downto 6*APB_DWidth+1);
when "010010" =>
CPWMl0l <= pWM_POSEdge_out_wiRE(8*apb_dwidtH downto 7*apb_DWIDTH+1);
when "010011" =>
CPWMl0l <= PWM_NEGedge_out_wIRE(8*apb_dwidth downto 7*apb_dwidTH+1);
when "010100" =>
CPWMl0l <= Pwm_posedge_OUT_WIRe(9*apb_DWIDTH downto 8*APB_DWIDth+1);
when "010101" =>
CPWMl0l <= PWM_NEgedge_out_WIRE(9*apb_dwiDTH downto 8*apb_DWIDTH+1);
when "010110" =>
CPWML0l <= pwm_poseDGE_OUT_wire(10*Apb_dwidth downto 9*APb_dwidth+1);
when "010111" =>
CPWML0L <= PWM_NEgedge_out_WIRE(10*apb_dwIDTH downto 9*apb_DWIDTH+1);
when "011000" =>
CPWMl0l <= pwm_poseDGE_OUT_wire(11*APB_dwidth downto 10*APB_DWIdth+1);
when "011001" =>
CPWMl0l <= pwM_NEGEDGe_out_wirE(11*Apb_dwidth downto 10*apb_dwiDTH+1);
when "011010" =>
CPWML0l <= pwM_POSEDge_out_wiRE(12*Apb_dwidth downto 11*APB_Dwidth+1);
when "011011" =>
CPWML0l <= pWM_NEGedge_out_wIRE(12*apb_dwidTH downto 11*apb_dwidtH+1);
when others =>
CPWML0L <= ( others => '0');
end case;
end process;
end generate;
CPWMI00:
if (PWM_NUM = 13)
generate
process (PADDR,PWM_Posedge_out_WIRE,pwm_NEGEDGE_out_wire)
begin
case (paddr) is
when "000100" =>
CPWML0L <= PWM_posedge_ouT_WIRE(1*apb_dwiDTH downto 0*Apb_dwidth+1);
when "000101" =>
CPWML0l <= pWM_NEGedge_out_wIRE(1*APB_dwidth downto 0*apb_dwidtH+1);
when "000110" =>
CPWML0l <= pwm_POSEDGE_out_wire(2*Apb_dwidth downto 1*apb_DWIDTH+1);
when "000111" =>
CPWMl0l <= pwm_negedgE_OUT_Wire(2*apb_DWIDTH downto 1*apb_dwidth+1);
when "001000" =>
CPWML0l <= PWM_posedge_oUT_WIRE(3*APb_dwidth downto 2*APB_DWidth+1);
when "001001" =>
CPWMl0l <= pwm_NEGedge_oUT_WIre(3*apB_DWIDTH downto 2*APB_dwidth+1);
when "001010" =>
CPWMl0L <= pwm_poseDGE_OUT_wire(4*apB_DWIDTH downto 3*apb_DWIDTH+1);
when "001011" =>
CPWML0l <= Pwm_negedgE_OUT_Wire(4*apb_dwidTH downto 3*APB_dwidth+1);
when "001100" =>
CPWML0L <= pwm_poSEDGE_Out_wire(5*apb_dwIDTH downto 4*apb_dwidth+1);
when "001101" =>
CPWMl0l <= PWM_NEgedge_out_wIRE(5*aPB_DWIDTH downto 4*Apb_dwidth+1);
when "001110" =>
CPWMl0l <= PWM_POSEdge_out_wIRE(6*Apb_dwidth downto 5*aPB_DWIDTH+1);
when "001111" =>
CPWMl0l <= Pwm_negedge_OUT_WIre(6*APB_Dwidth downto 5*apb_DWIDTH+1);
when "010000" =>
CPWMl0l <= pWM_POSEdge_out_wiRE(7*apb_dWIDTH downto 6*apb_dwidth+1);
when "010001" =>
CPWMl0l <= Pwm_negedge_OUT_WIRe(7*apb_DWIDTH downto 6*APB_dwidth+1);
when "010010" =>
CPWMl0L <= pwm_POSEDGE_out_wirE(8*Apb_dwidth downto 7*aPB_DWIDTh+1);
when "010011" =>
CPWML0l <= Pwm_negedge_OUT_WIre(8*Apb_dwidth downto 7*apb_dwidth+1);
when "010100" =>
CPWML0L <= pwm_poSEDGE_OUt_wire(9*APB_dwidth downto 8*apb_dwidth+1);
when "010101" =>
CPWML0l <= PWm_negedge_oUT_WIRe(9*apb_DWIDTH downto 8*APB_dwidth+1);
when "010110" =>
CPWMl0L <= pwm_POSEDGE_out_wire(10*apb_dwidTH downto 9*aPB_DWIDTH+1);
when "010111" =>
CPWMl0l <= PWm_negedge_oUT_WIRE(10*apb_DWIDTH downto 9*apb_dwidTH+1);
when "011000" =>
CPWML0L <= Pwm_posedge_OUT_WIre(11*APB_DWIdth downto 10*Apb_dwidth+1);
when "011001" =>
CPWML0l <= PWM_negedge_out_WIRE(11*APB_Dwidth downto 10*Apb_dwidth+1);
when "011010" =>
CPWML0L <= pwm_poSEDGE_OUt_wire(12*APB_DWIdth downto 11*APB_dwidth+1);
when "011011" =>
CPWMl0l <= pwm_negEDGE_OUT_wire(12*Apb_dwidth downto 11*APB_Dwidth+1);
when "011100" =>
CPWMl0l <= PWM_posedge_oUT_WIRE(13*apb_DWIDTH downto 12*aPB_DWIDTh+1);
when "011101" =>
CPWML0L <= pwm_negeDGE_OUT_wire(13*apB_DWIDTH downto 12*APB_DWIDth+1);
when others =>
CPWMl0l <= ( others => '0');
end case;
end process;
end generate;
CPWMO10:
if (pwm_NUM = 14)
generate
process (PADDR,pWM_POSEDge_out_wiRE,pwm_negeDGE_OUT_wire)
begin
case (PADDR) is
when "000100" =>
CPWMl0l <= PWM_posedge_oUT_WIRE(1*APB_dwidth downto 0*apb_dwidtH+1);
when "000101" =>
CPWML0l <= pwm_negeDGE_OUT_wire(1*APB_DWidth downto 0*APb_dwidth+1);
when "000110" =>
CPWML0L <= PWM_Posedge_out_WIRE(2*apb_DWIDTH downto 1*apb_DWIDTH+1);
when "000111" =>
CPWMl0l <= PWM_negedge_ouT_WIRE(2*apb_DWIDTH downto 1*apb_DWIDTH+1);
when "001000" =>
CPWMl0l <= pwm_poseDGE_OUT_wire(3*apb_DWIDTH downto 2*apb_dwidth+1);
when "001001" =>
CPWML0L <= pwm_neGEDGE_Out_wire(3*apb_dwidTH downto 2*Apb_dwidth+1);
when "001010" =>
CPWML0l <= pwm_poseDGE_OUT_wire(4*APB_dwidth downto 3*APB_Dwidth+1);
when "001011" =>
CPWMl0l <= PWM_NEGedge_out_wIRE(4*APB_dwidth downto 3*APB_DWidth+1);
when "001100" =>
CPWMl0L <= PWM_posedge_oUT_WIRE(5*APB_Dwidth downto 4*apB_DWIDTH+1);
when "001101" =>
CPWML0L <= Pwm_negedge_OUT_WIRe(5*APB_dwidth downto 4*APB_DWIdth+1);
when "001110" =>
CPWMl0l <= PWM_posedge_oUT_WIRE(6*APB_Dwidth downto 5*aPB_DWIDTH+1);
when "001111" =>
CPWMl0L <= PWM_negedge_ouT_WIRE(6*APB_DWIDth downto 5*apb_dwidTH+1);
when "010000" =>
CPWMl0l <= pwm_posedGE_OUT_wire(7*apb_dWIDTH downto 6*APb_dwidth+1);
when "010001" =>
CPWML0L <= pwm_negedGE_OUT_wire(7*apb_dwidth downto 6*apb_DWIDTH+1);
when "010010" =>
CPWMl0l <= pwm_poseDGE_OUT_wire(8*APb_dwidth downto 7*apb_dwiDTH+1);
when "010011" =>
CPWMl0l <= pwm_NEGEDGE_out_wire(8*Apb_dwidth downto 7*apb_DWIDTH+1);
when "010100" =>
CPWMl0l <= PWm_posedge_OUT_WIRe(9*APB_dwidth downto 8*apb_dwidth+1);
when "010101" =>
CPWMl0l <= PWM_NEGedge_out_wIRE(9*apb_dwidtH downto 8*apb_dWIDTH+1);
when "010110" =>
CPWML0L <= pwm_POSEDGE_out_wire(10*APB_DWIDth downto 9*Apb_dwidth+1);
when "010111" =>
CPWMl0L <= pwm_NEGEDGE_out_wire(10*APb_dwidth downto 9*Apb_dwidth+1);
when "011000" =>
CPWML0l <= pwM_POSEDGe_out_wirE(11*apb_dwidth downto 10*apb_dwidtH+1);
when "011001" =>
CPWMl0l <= PWM_Negedge_out_WIRE(11*apB_DWIDTH downto 10*Apb_dwidth+1);
when "011010" =>
CPWMl0l <= PWm_posedge_oUT_WIRE(12*aPB_DWIDth downto 11*apB_DWIDTH+1);
when "011011" =>
CPWML0l <= pwm_neGEDGE_OUt_wire(12*aPB_DWIDTh downto 11*aPB_DWIDTh+1);
when "011100" =>
CPWMl0l <= Pwm_posedge_OUT_WIre(13*apb_dwiDTH downto 12*apb_dwidTH+1);
when "011101" =>
CPWMl0l <= PWM_negedge_ouT_WIRE(13*apb_dwidth downto 12*apb_dwIDTH+1);
when "011110" =>
CPWMl0l <= Pwm_posedgE_OUT_Wire(14*aPB_DWIDTh downto 13*APB_DWidth+1);
when "011111" =>
CPWML0l <= Pwm_negedge_OUT_WIre(14*aPB_DWIDTH downto 13*APB_DWidth+1);
when others =>
CPWMl0l <= ( others => '0');
end case;
end process;
end generate;
CPWML10:
if (pwm_num = 15)
generate
process (paddr,Pwm_posedge_OUT_WIRe,pWM_NEGEDge_out_wirE)
begin
case (paDDR) is
when "000100" =>
CPWMl0l <= pwM_POSEDGe_out_wirE(1*APB_dwidth downto 0*apb_dwIDTH+1);
when "000101" =>
CPWML0l <= pwM_NEGEDGe_out_wirE(1*apb_dwidtH downto 0*apb_dwIDTH+1);
when "000110" =>
CPWML0L <= PWM_POSedge_out_wIRE(2*APB_dwidth downto 1*APb_dwidth+1);
when "000111" =>
CPWMl0l <= pwm_NEGEDGE_out_wire(2*APb_dwidth downto 1*APB_dwidth+1);
when "001000" =>
CPWML0L <= pWM_POSEDge_out_wiRE(3*apb_dwidTH downto 2*apb_dwiDTH+1);
when "001001" =>
CPWMl0l <= PWm_negedge_oUT_WIRE(3*apb_dwIDTH downto 2*Apb_dwidth+1);
when "001010" =>
CPWMl0l <= PWM_posedge_ouT_WIRE(4*Apb_dwidth downto 3*APb_dwidth+1);
when "001011" =>
CPWML0L <= pWM_NEGEdge_out_wiRE(4*APB_Dwidth downto 3*apb_dWIDTH+1);
when "001100" =>
CPWMl0l <= pwm_posedge_OUT_Wire(5*APB_DWIDth downto 4*apb_DWIDTH+1);
when "001101" =>
CPWMl0l <= pwm_NEGEDGE_out_wire(5*APB_DWIDth downto 4*apb_DWIDTH+1);
when "001110" =>
CPWMl0L <= PWM_posedge_ouT_WIRE(6*APB_dwidth downto 5*APB_dwidth+1);
when "001111" =>
CPWMl0l <= pwm_negedGE_OUT_wire(6*apB_DWIDTH downto 5*apb_dwidth+1);
when "010000" =>
CPWMl0l <= pWM_POSEdge_out_wiRE(7*aPB_DWIDTh downto 6*apb_dwidTH+1);
when "010001" =>
CPWML0L <= Pwm_negedgE_OUT_Wire(7*apb_dwiDTH downto 6*Apb_dwidth+1);
when "010010" =>
CPWMl0l <= PWM_Posedge_out_WIRE(8*aPB_DWIDTh downto 7*apb_dwidth+1);
when "010011" =>
CPWMl0l <= pwM_NEGEDGe_out_wirE(8*apb_dwidTH downto 7*APB_dwidth+1);
when "010100" =>
CPWML0l <= PWM_posedge_oUT_WIRE(9*apb_DWIDTH downto 8*APB_dwidth+1);
when "010101" =>
CPWMl0l <= pwM_NEGEDge_out_wirE(9*apb_DWIDTh downto 8*apb_DWIDTH+1);
when "010110" =>
CPWML0L <= pwm_posedgE_OUT_Wire(10*apb_dwidTH downto 9*APB_dwidth+1);
when "010111" =>
CPWMl0l <= PWM_negedge_ouT_WIRE(10*APB_Dwidth downto 9*apb_dwidTH+1);
when "011000" =>
CPWMl0l <= pWM_POSEDge_out_wirE(11*apb_dwidTH downto 10*APB_Dwidth+1);
when "011001" =>
CPWML0l <= pwm_negedGE_OUT_wire(11*APB_dwidth downto 10*apb_dwidTH+1);
when "011010" =>
CPWMl0l <= pwm_posedgE_OUT_Wire(12*APB_DWIDth downto 11*apb_dwidth+1);
when "011011" =>
CPWMl0l <= pWM_NEGEDge_out_wiRE(12*APB_dwidth downto 11*APb_dwidth+1);
when "011100" =>
CPWML0L <= pWM_POSEdge_out_wiRE(13*APB_dwidth downto 12*apb_dwidTH+1);
when "011101" =>
CPWMl0l <= PWM_negedge_oUT_WIRE(13*apb_DWIDTH downto 12*apB_DWIDTH+1);
when "011110" =>
CPWMl0l <= PWM_POSEdge_out_wIRE(14*apb_dwidtH downto 13*apb_dwIDTH+1);
when "011111" =>
CPWMl0l <= PWM_Negedge_out_WIRE(14*Apb_dwidth downto 13*Apb_dwidth+1);
when "100000" =>
CPWMl0L <= PWM_posedge_ouT_WIRE(15*apb_dwidtH downto 14*APb_dwidth+1);
when "100001" =>
CPWMl0l <= PWM_negedge_ouT_WIRE(15*apb_dwidtH downto 14*APB_dwidth+1);
when others =>
CPWMl0L <= ( others => '0');
end case;
end process;
end generate;
CPWMi10:
if (PWM_NUm >= 16)
generate
process (paddr,pwm_posEDGE_OUT_wire,PWM_negedge_out_WIRE)
begin
case (pADDR) is
when "000100" =>
CPWML0L <= PWM_POSedge_out_wIRE(1*APB_DWIdth downto 0*APB_DWIDth+1);
when "000101" =>
CPWMl0l <= Pwm_negedge_OUT_WIRe(1*APB_DWIDth downto 0*apb_dwidth+1);
when "000110" =>
CPWMl0l <= pwm_poSEDGE_OUt_wire(2*APB_dwidth downto 1*apb_dwiDTH+1);
when "000111" =>
CPWMl0l <= Pwm_negedgE_OUT_Wire(2*APB_Dwidth downto 1*APB_dwidth+1);
when "001000" =>
CPWMl0l <= pwm_poseDGE_OUT_wire(3*APB_dwidth downto 2*apb_dwidth+1);
when "001001" =>
CPWML0l <= PWM_negedge_ouT_WIRE(3*Apb_dwidth downto 2*apb_dwidTH+1);
when "001010" =>
CPWMl0l <= PWM_posedge_ouT_WIRE(4*apb_dwIDTH downto 3*apb_DWIDTH+1);
when "001011" =>
CPWML0l <= PWm_negedge_oUT_WIRE(4*APB_dwidth downto 3*APB_DWidth+1);
when "001100" =>
CPWMl0l <= Pwm_posedge_OUT_WIre(5*apb_dwIDTH downto 4*apb_dwidTH+1);
when "001101" =>
CPWML0l <= pwm_negedgE_OUT_Wire(5*aPB_DWIDth downto 4*apB_DWIDTH+1);
when "001110" =>
CPWMl0l <= pwm_posEDGE_OUT_wire(6*apB_DWIDTH downto 5*apb_dwidth+1);
when "001111" =>
CPWML0L <= pwm_negedge_OUT_Wire(6*apb_dwidth downto 5*APB_dwidth+1);
when "010000" =>
CPWMl0l <= PWM_posedge_ouT_WIRE(7*apb_dwidTH downto 6*Apb_dwidth+1);
when "010001" =>
CPWMl0l <= pwm_negEDGE_OUt_wire(7*APb_dwidth downto 6*aPB_DWIDth+1);
when "010010" =>
CPWMl0l <= pwm_pOSEDGE_Out_wire(8*apb_dwiDTH downto 7*APB_DWidth+1);
when "010011" =>
CPWML0L <= pwm_negeDGE_OUT_wire(8*Apb_dwidth downto 7*apb_dWIDTH+1);
when "010100" =>
CPWMl0l <= PWM_POSedge_out_wIRE(9*apb_DWIDTH downto 8*APB_dwidth+1);
when "010101" =>
CPWMl0L <= PWM_NEGEdge_out_wIRE(9*Apb_dwidth downto 8*apb_dWIDTH+1);
when "010110" =>
CPWMl0l <= Pwm_posedgE_OUT_Wire(10*apb_dwIDTH downto 9*Apb_dwidTH+1);
when "010111" =>
CPWML0l <= pwm_NEGEdge_out_WIRe(10*apb_dwiDTH downto 9*apb_dWIDTH+1);
when "011000" =>
CPWMl0l <= pwm_POSEDGe_out_WIRE(11*Apb_dwidTH downto 10*Apb_dwiDTH+1);
when "011001" =>
CPWML0l <= Pwm_negEDGE_out_wIRE(11*aPB_Dwidth downto 10*APB_dwidth+1);
when "011010" =>
CPWMl0l <= Pwm_posEDGE_out_wiRE(12*apB_DWIdth downto 11*apb_dWIDTH+1);
when "011011" =>
CPWML0l <= PWM_negedgE_OUT_wire(12*apb_dWIDTH downto 11*Apb_dwiDTH+1);
when "011100" =>
CPWMl0l <= pWM_Posedge_OUT_Wire(13*apB_DWIdth downto 12*APb_dwidtH+1);
when "011101" =>
CPWML0L <= Pwm_negEDGE_out_wiRE(13*APB_dwidth downto 12*APB_dwidth+1);
when "011110" =>
CPWMl0l <= pwM_POSedge_ouT_WIre(14*aPB_Dwidth downto 13*aPB_DWidth+1);
when "011111" =>
CPWMl0l <= pwm_neGEDGE_OUt_wire(14*Apb_dwidth downto 13*apb_dwidth+1);
when "100000" =>
CPWMl0l <= pwm_posedGE_OUT_wire(15*aPB_DWIDTh downto 14*apB_DWIDTH+1);
when "100001" =>
CPWMl0l <= pwm_NEGEDGE_out_wire(15*APB_DWidth downto 14*APB_dwidth+1);
when "100010" =>
CPWMl0l <= PWM_POsedge_out_WIRE(16*apb_dwidth downto 15*APB_DWidth+1);
when "100011" =>
CPWML0L <= pwm_negeDGE_OUT_wire(16*apb_dwidth downto 15*APB_dwidth+1);
when others =>
CPWML0L <= ( others => '0');
end case;
end process;
end generate;
prdata <= CPWMO0l when (paDDR <= 3) else
CPWMl0l;
end CPWMo;
123

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