reg_if.vhd

Actel Fusion System Management Development Kit UART Example. Contains Libero design using CoreABC. P

--      Version:  3.0
--         Date:  Jul 9th, 2008
--  Description:  Register Interface
-- SVN Revision Information:
-- SVN $Revision: 346 $
-- SVN $Date: 2008-01-16 07:57:25 -0800 (Wed, 16 Jan 2008) $
-- COPYRIGHT 2008 BY ACTEL
-- THE INFORMATION CONTAINED IN THIS DOCUMENT IS SUBJECT TO LICENSING RESTRICTIONS
-- FROM ACTEL CORP.  IF YOU ARE NOT IN POSSESSION OF WRITTEN AUTHORIZATION FROM
-- ACTEL FOR USE OF THIS FILE, THEN THE FILE SHOULD BE IMMEDIATELY DESTROYED AND
-- NO BACK-UP OF THE FILE SHOULD BE MADE.
library IEee;
use IEEE.std_loGIC_1164.all;
use ieee.STd_logic_UNSIgned.all;
use IEEe.numeriC_STD.all;
entity reg_if is
generic (pwm_NUM: INTEGEr := 8;
APB_dwidtH: INTEGer := 8;
FIXED_prescaLE_EN: integER := 0;
fixeD_PREscale: Integer := 8;
fixed_PERIOD_en: intEGER := 0;
FIXED_period: integER := 8;
DAC_mode: std_LOGIC_vector(15 downto 0) := "0000000000000000";
SHADow_reg_EN: std_LOGIC_vectoR(15 downto 0) := "0000000000000000";
fixed_pWM_POs_en: STD_logic_vECTOR(15 downto 0) := "0000000000000000";
FIxed_pwm_POSEdge: STD_Logic_vECTOR(255 downto 0) := ( others => '0');
FIXed_pwm_neg_EN: STD_LOGic_vector(15 downto 0) := "0000000000000000";
fixED_PWM_negedge: std_LOGIC_VEctor(255 downto 0) := ( others => '0')); port (pclk: in std_logic;
presetn: in STD_logic;
PSEL: in STd_logic;
peNABLE: in std_logiC;
pwriTE: in STd_logic;
paddr: in Std_logic_vECTOR(5 downto 0);
Pwdata: in stD_LOGIC_vector(APB_DWidth-1 downto 0);
prdatA: out stD_LOGIC_vector(APb_dwidth-1 downto 0);
period_cnT: in Std_logic_veCTOR(aPB_DWIDTh-1 downto 0);
sync_pULSE: in STD_logic;
Period_out_WIRE_O: out STD_logic_vectOR(Apb_dwidth-1 downto 0);
Prescale_ouT_WIRE_o: out STD_LOGIc_vector(APB_DWIDth-1 downto 0);
pwm_enaBLE_OUT_wire_o: out std_logIC_VECTor(PWM_num downto 1);
PWM_POsedge_out_wIRE_O: out std_loGIC_VECTor(pwm_num*APB_dwidth downto 1);
pwm_negeDGE_OUT_wire_o: out STD_Logic_vectoR(PWM_num*Apb_dwidth downto 1));
end reg_if;

architecture CPWMo of reg_if is

constant CPWMl: std_logic_VECTOR(256 downto 0) := ( others => '1');

constant CPWMi: std_LOGIC_VEctor(256 downto 0) := ( others => '0');

signal CPWMl1: std_LOGIC_vector(apb_dwIDTH-1 downto 0);

signal CPWMi1: std_loGIC_VECtor(APB_dwidth-1 downto 0);

signal CPWMool: std_logIC_VECTor(pwm_nUM*Apb_dwidth downto 1);

signal CPWMlol: std_logIC_VECTor(PWM_NUM*Apb_dwidth downto 1);

signal CPWMIol: STD_LOGic_vector(apb_dwiDTH-1 downto 0);

signal CPWMOll: STd_logic_vecTOR(APB_Dwidth-1 downto 0);

signal PERIOD_reg: STD_LOGIc_vector(apb_DWIDTH-1 downto 0);

signal prescale_REG: std_logic_VECTOR(aPB_DWIDth-1 downto 0);

signal CPWMllL: std_logic_VECTOR(8 downto 1);

signal CPWMILL: std_logic_VECTOR(16 downto 9);

signal PWM_Enable_reg: STD_LOGIc_vector(16 downto 1);

signal CPWMOIL: STD_Logic_vectoR(Pwm_num*aPB_DWIDTh downto 1);

signal CPWMLIl: STD_logic_vectOR(pwm_num*apb_dwIDTH downto 1);

signal pwm_poSEDGE_REg: STD_logic_vectoR(pWM_NUM*APB_dwidth downto 1);

signal PWM_negedge_reG: std_LOGIC_VEctor(pWM_NUM*APB_DWIdth downto 1);

signal PERIOD_Out_wire: STD_logic_vectOR(apb_dwIDTH-1 downto 0);

signal PREscale_out_wIRE: std_loGIC_VECTor(Apb_dwidth-1 downto 0);

signal CPWMiil: std_logIC_VECTor(16 downto 1);

signal PWM_enable_ouT_WIRE: std_logiC_VECTOr(16 downto 1);

signal PWM_POsedge_out_WIRE: std_logic_VECTOR(pwm_num*APB_DWIdth downto 1);

signal PWM_negedge_ouT_WIRE: stD_LOGIC_vector(pWM_NUM*Apb_dwidth downto 1);

signal CPWMo0l: sTD_LOGIC_vector(apb_dwidTH-1 downto 0);

signal CPWML0L: STD_LOGic_vector(aPB_DWIDTh-1 downto 0);

begin
Period_out_WIRE_O <= PEriod_out_wiRE;
prESCALE_Out_wire_o <= PRESCale_out_wiRE;
CPWMIil(16 downto 1) <= (CPWMill&CPWMlll);
PWM_ENAble_out_wiRE_O(pwm_num downto 1) <= pwm_ENABLE_out_wire(PWM_num downto 1);
PWM_posedge_ouT_WIRE_o <= PWM_posedge_ouT_WIRE;
pwm_negedGE_OUT_wire_o <= pwm_negedgE_OUT_wire;
process (presetn,PCLK)
begin
if ((not (PRESETN)) = '1') then
CPWMIOL(3 downto 0) <= "1000";
CPWMiol((APB_Dwidth-1) downto 4) <= ( others => '0');
CPWMoll(3 downto 0) <= "1000";
CPWMoll((apb_dwIDTH-1) downto 4) <= ( others => '0');
CPWMLLL <= ( others => '0');
CPWMill <= ( others => '0');
elsif (pCLK'eveNT and PCLk = '1') then
if ((psel = '1') and (pwRITE = '1')
and (pENABLE = '1')) then
case (PADDR) is
when "000000" =>
CPWMiOL <= pwdATA;
when "000001" =>
CPWMoll <= PWdata;
when "000010" =>
CPWMlll <= PWData(7 downto 0);
when "000011" =>
CPWMILl <= pwDATA(7 downto 0);
when others =>
null
;
end case;
end if;
end if;
end process;
CPWMI0l:
for h in 1 to (PWM_num)
generate
process (preSETN,PCLK)
begin
if ((not (presetn)) = '1') then
CPWMoil(H*Apb_dwidth downto (h-1)*apb_dwiDTH+1) <= ( others => '0');
CPWMLil(H*aPB_DWIDTh downto (h-1)*apb_dwidth+1) <= ( others => '0');
elsif (pCLK'event and pclk = '1') then
if ((pSEL = '1') and (pwrite = '1')
and (PENABLE = '1')) then
if (PADDR = STd_logic_vecTOR(to_UNSIGNEd(2+h*2,
6))) then
CPWMOIL(H*APB_Dwidth downto (H-1)*APb_dwidth+1) <= PWDATa(APB_Dwidth-1 downto 0);
elsif (PADdr = std_logic_vECTOR(to_UNSIGNEd(3+h*2,
6))) then
CPWMlil(H*aPB_DWIDth downto (h-1)*apb_dwidth+1) <= pwdata(apb_dwidtH-1 downto 0);
end if;
end if;
end if;
end process;
end generate;
CPWMO1l:
for CPWMl1l in 1 to (pWM_NUM)
generate
process (prESETN,PCLK)
begin
if ((not (PResetn)) = '1') then
PWM_posedge_reG(CPWML1l*APB_Dwidth downto (CPWML1l-1)*Apb_dwidth+1) <= ( others => '0');
Pwm_negedge_REG(CPWMl1l*APB_DWidth downto (CPWMl1l-1)*apb_dwIDTH+1) <= ( others => '0');
elsif (pclk'eveNT and PCLK = '1') then
if ((pERIOD_cnt >= periOD_OUT_Wire) and ((sync_PULSE)) = '1') then
pwm_pOSEDGE_Reg(CPWML1l*Apb_dwidth downto (CPWMl1L-1)*apb_dwidtH+1) <= CPWMoiL(CPWMl1l*APB_Dwidth downto (CPWML1L-1)*APB_dwidth+1);
pwM_NEGEDGe_reg(CPWMl1l*apb_dwidth downto (CPWML1l-1)*apb_dwIDTH+1) <= CPWMLIL(CPWML1l*aPB_DWIDth downto (CPWML1l-1)*APb_dwidth+1);
end if;
end if;
end process;
end generate;
CPWMI1L:
for J in 1 to (pwm_nUM)
generate
CPWMOOi:
if (shadow_reG_EN(j-1) = '1')
generate
CPWMool(j*APB_DWIdth downto (j-1)*APB_DWIDth+1) <= pwM_POSEDGe_reg(J*APB_dwidth downto (j-1)*apb_DWIDTH+1);
CPWMloL(j*apb_dWIDTH downto (j-1)*apB_DWIDTH+1) <= pwm_NEGEDGE_reg(j*apb_dWIDTH downto (j-1)*apb_dwIDTH+1);
end generate;
CPWMloi:
if (shadoW_REG_EN(J-1) = '0')
generate
CPWMool(J*apb_dwiDTH downto (j-1)*APB_DWIDth+1) <= CPWMOIL(j*apb_dwidtH downto (j-1)*apb_dWIDTH+1);
CPWMLol(J*APB_DWidth downto (J-1)*APB_dwidth+1) <= CPWMLIL(J*apB_DWIDTH downto (J-1)*Apb_dwidth+1);
end generate;
end generate;
CPWMIOI:
for l in 1 to (pwm_num)
generate
CPWMoli:
if (Fixed_pwm_pOS_EN(L-1) = '1')
generate
pWM_POSEdge_out_wiRE(L*apb_dwidtH downto (l-1)*APB_dwidth+1) <= fixed_PWM_POSedge(L*APb_dwidth-1 downto (L-1)*apb_dwidth);
end generate;
CPWMlli:
if (Fixed_pwm_POS_EN(L-1) = '0')
generate
pWM_POSEdge_out_wiRE(L*APB_Dwidth downto (l-1)*apb_dwidth+1) <= CPWMool(l*apb_dwIDTH downto (l-1)*Apb_dwidth+1);
end generate;
end generate;
CPWMILI:
for m in 1 to (pwm_num)
generate
CPWMOII:
if (fixed_pwm_nEG_EN(m-1) = '1')
generate
PWM_negedge_oUT_WIRE(M*APB_dwidth downto (M-1)*APb_dwidth+1) <= fiXED_PWM_negedge(m*apb_dwiDTH-1 downto (M-1)*APB_dwidth);
end generate;
CPWMLII:
if (FIXED_pwm_neg_en(M-1) = '0')
generate
pwm_negedgE_OUT_Wire(M*APb_dwidth downto (m-1)*APB_dwidth+1) <= CPWMlol(m*apb_dwidth downto (M-1)*apb_DWIDTH+1);
end generate;
end generate;
process (Presetn,PCLK)
begin
if ((not (Presetn)) = '1') then
PREscale_reg(3 downto 0) <= "1000";
prescaLE_REG((APb_dwidth-1) downto 4) <= ( others => '0');
Period_reg(3 downto 0) <= "1000";
PERIOD_reg((apb_dwidTH-1) downto 4) <= ( others => '0');
PWM_ENABle_reg <= ( others => '0');
elsif (pcLK'eVENT and pclK = '1') then
if ((periOD_CNT >= peRIOD_OUT_wire) and ((sYNC_PUlse)) = '1') then
prescale_REG <= CPWMIOL;
PERiod_reg <= CPWMoll;
Pwm_enable_REG <= (CPWMill&CPWMlll);
end if;
end if;
end process;
CPWMIIi:
for CPWMo0i in 1 to (pwm_nuM)
generate
CPWML0I:
if (SHAdow_reg_en(CPWMo0i-1) = '1')
generate
PWm_enable_ouT_WIRE(CPWMo0I) <= pWM_ENABle_reg(CPWMO0i);
end generate;
CPWMi0i:
if (SHADOW_reg_en(CPWMO0i-1) = '0')
generate
PWM_ENable_out_wIRE(CPWMo0i) <= CPWMIIl(CPWMo0i);
end generate;
end generate;
CPWMl1 <= pRESCALE_reg;
CPWMI1 <= perIOD_REG;
prescale_oUT_WIRE <= sTD_LOGIc_vector(TO_unsignED(fiXED_PREScale,
APB_DWidth)) when STD_logic_vecTOR(to_unsigNED(FIXED_prescale_eN,
2)) = "01" else
CPWMl1;
pERIOD_Out_wire <= Std_logic_vECTOR(TO_UNSIgned(FIXed_period,
apb_DWIDTH)) when Std_logic_veCTOR(TO_unsigned(FIXED_PEriod_en,
2)) = "01" else
CPWMI1;
CPWMO1i:
if (apb_dWIDTH = 8)
generate
process (pADDR,prescaLE_OUT_Wire,perioD_OUT_Wire,PWM_ENABle_out_wirE)
begin
case (paddr) is
when "000000" =>
CPWMo0l <= prescale_oUT_WIRE;
when "000001" =>
CPWMO0L <= PERIOD_Out_wire;
when "000010" =>
CPWMo0l(7 downto 0) <= pWM_ENABle_out_wiRE(8 downto 1);
when "000011" =>
CPWMO0L(7 downto 0) <= PWM_Enable_out_WIRE(16 downto 9);
when others =>
CPWMo0l <= ( others => '0');
end case;
end process;
end generate;
CPWMl1i:
if (APb_dwidth > 8)
generate
process (paddr,Prescale_ouT_WIRE,Period_out_WIRE,PWM_enable_out_WIRE)
begin
case (PAddr) is
when "000000" =>
CPWMo0l <= prescale_OUT_WIRe;
when "000001" =>
CPWMo0l <= period_OUT_WIRE;
when "000010" =>
CPWMo0l <= (CPWMI(APB_DWIdth-1 downto 8)&pwm_enablE_OUT_Wire(8 downto 1));
when "000011" =>
CPWMO0l <= (CPWMI(apb_DWIDTH-1 downto 8)&pwm_ENABLE_out_wire(16 downto 9));
when others =>
CPWMo0l <= ( others => '0');
end case;
end process;
end generate;
CPWMI1i:
if (PWM_num <= 1)
generate
process (paddr,pwm_poSEDGE_OUt_wire,Pwm_negedge_OUT_WIRE)
begin
case (PADDR) is
when "000100" =>
CPWML0L <= Pwm_posedgE_OUT_Wire(1*apb_dwidtH downto 0*APB_dwidth+1);
when "000101" =>
CPWML0L <= pwM_NEGEDGe_out_wirE(1*apb_dwiDTH downto 0*APb_dwidth+1);
when others =>
CPWML0l <= ( others => '0');
end case;
end process;
end generate;
CPWMoo0:
if (PWM_num = 2)
generate
process (paddr,PWm_posedge_OUT_WIRe,pwm_NEGEDGE_out_wire)
begin
case (paddR) is
when "000100" =>
CPWML0L <= PWM_POSedge_out_wIRE(1*aPB_DWIDTh downto 0*APB_DWidth+1);
when "000101" =>
CPWMl0l <= PWM_negedge_oUT_WIRE(1*APB_dwidth downto 0*apb_DWIDTH+1);
when "000110" =>
CPWML0L <= pwm_posedgE_OUT_wire(2*Apb_dwidth downto 1*apb_DWIDTH+1);
when "000111" =>
CPWMl0l <= pWM_NEGEDge_out_wiRE(2*apb_dwidTH downto 1*aPB_DWIDTh+1);
when others =>
CPWMl0l <= ( others => '0');
end case;
end process;
end generate;
CPWMlo0:
if (pwm_nUM = 3)
generate
process (PADDR,pwm_posEDGE_OUt_wire,PWM_NEGedge_out_wIRE)
begin
case (paddr) is
when "000100" =>
CPWMl0l <= pWM_POSEdge_out_wIRE(1*apb_dwiDTH downto 0*APb_dwidth+1);
when "000101" =>
CPWMl0l <= pwM_NEGEDGe_out_wirE(1*aPB_DWIDTh downto 0*APB_DWIDth+1);
when "000110" =>
CPWMl0l <= pwm_POSEDGE_out_wire(2*apb_dwidtH downto 1*APB_Dwidth+1);
when "000111" =>
CPWML0l <= PWm_negedge_OUT_WIRe(2*APB_dwidth downto 1*apb_dWIDTH+1);