pwm_gen.vhd

Actel Fusion System Management Development Kit UART Example. Contains Libero design using CoreABC. P

--      Version:  3.0
--         Date:  May 14th, 2008
--  Description:  PWM Generation Module
-- SVN Revision Information:
-- SVN $Revision: 346 $
-- SVN $Date: 2008-01-16 07:57:25 -0800 (Wed, 16 Jan 2008) $  
-- COPYRIGHT 2008 BY ACTEL 
-- THE INFORMATION CONTAINED IN THIS DOCUMENT IS SUBJECT TO LICENSING RESTRICTIONS 
-- FROM ACTEL CORP.  IF YOU ARE NOT IN POSSESSION OF WRITTEN AUTHORIZATION FROM 
-- ACTEL FOR USE OF THIS FILE, THEN THE FILE SHOULD BE IMMEDIATELY DESTROYED AND 
-- NO BACK-UP OF THE FILE SHOULD BE MADE. 
library iEEE;
use IEEE.STD_logic_1164.all;
use ieee.Numeric_std.all;
use ieee.std_logic_ARITH.all;
use ieee.sTD_LOGIC_unsigned.all;
entity PWM_gen is
generic (pwm_num: integer := 1;
APB_DWIDth: integER := 8;
DAC_MODE: STD_LOgic_vector(15 downto 0) := "0000000000000000"); port (PRESETn: in stD_LOGIC;
pCLK: in STD_logic;
PWM: out sTD_LOGIC_vector(pwm_num downto 1);
PERIOD_Cnt: in Std_logic_VECTOR(Apb_dwidth-1 downto 0);
pwm_enabLE_REG: in STD_LOGIc_vector(pwm_NUM downto 1);
PWM_POsedge_reg: in STD_logic_vectOR((Pwm_num*aPB_DWIDTH) downto 1);
pwM_NEGEDGe_reg: in STd_logic_vecTOR((PWM_Num*APB_dwidth) downto 1);
sync_PULSE: in STD_logic);
end Pwm_gen;

architecture CPWMo of PWM_gen is

signal CPWMiI: STD_LOgic_vector(PWM_NUm downto 1);

signal CPWMo0: STD_logic_vecTOR(PWM_NUM*(apB_DWIDth+1) downto 1);

begin
pwM(PWM_NUM downto 1) <= CPWMii(PWM_num downto 1);
CPWML0:
for z in 1 to Pwm_num
generate
CPWMi0:
if (dac_moDE(Z-1) = '0')
generate
process (PResetn,PClk)
begin
if ((not (presETN)) = '1') then
CPWMii(Z) <= '0';
elsif (Pclk'evENT and PCLK = '1') then
if (PWM_enable_reg(z) = '0') then
CPWMii(z) <= '0';
elsif ((pwM_ENABle_reg(z) = '1') and (Sync_pulse = '1')) then
if ((PWM_Posedge_reg(Z*aPB_DWIDTh downto (z-1)*Apb_dwidth+1) = Pwm_negedge_REG(Z*apb_DWIDTH downto (z-1)*Apb_dwidth+1)) and ((PWM_POSEdge_reg(z*apb_DWIDTH downto (Z-1)*APb_dwidth+1)) = perIOD_CNT)) then
CPWMii(z) <= not (CPWMII(Z));
elsif ((pwm_enable_REG(z) = '1') and (SYNC_PUlse = '1')
and (pwm_pOSEDGE_Reg(z*apb_dwIDTH downto (Z-1)*apb_dwidth+1)) = PERiod_cnt) then
CPWMII(z) <= '1';
elsif ((PWM_Enable_reg(Z) = '1') and (sync_pulSE = '1')
and (PWM_negedge_rEG(z*APB_dwidth downto (Z-1)*APB_DWIdth+1)) = Period_cnt) then
CPWMii(z) <= '0';
end if;
end if;
end if;
end process;
end generate;
CPWMo1:
if (not (DAC_MODe(z-1) = '0'))
generate
process (Presetn,PCLK)
begin
if ((not (preseTN)) = '1') then
CPWMO0(z*(APB_dwidth+1) downto (Z-1)*(apb_dWIDTH+1)+1) <= ( others => '0');
CPWMii(z) <= '0';
elsif (pcLK'EVENT and PCLk = '1') then
if (pwM_ENABLe_reg(Z) = '0') then
CPWMii(Z) <= '0';
elsif (pwm_eNABLE_Reg(z) = '1') then
CPWMo0(Z*(APB_DWidth+1) downto (z-1)*(APB_DWIdth+1)+1) <= ('0'&CPWMo0((z*(APB_DWidth+1))-1 downto (Z-1)*(aPB_DWIDth+1)+1)+pWM_NEGEDge_reg(Z*APB_dwidth downto ((z-1)*APb_dwidth)+1));
CPWMii(z) <= CPWMo0(z*(Apb_dwidth+1));
end if;
end if;
end process;
end generate;
end generate;
end CPWMo;