timebase.vhd

Actel Fusion System Management Development Kit UART Example. Contains Libero design using CoreABC. P

--      Version:  3.0
--         Date:  Jun 14th, 2007
--  Description:  Timebase module
-- SVN Revision Information:
-- SVN $Revision: 346 $
-- SVN $Date: 2008-01-16 07:57:25 -0800 (Wed, 16 Jan 2008) $  
-- COPYRIGHT 2007 BY ACTEL 
-- THE INFORMATION CONTAINED IN THIS DOCUMENT IS SUBJECT TO LICENSING RESTRICTIONS 
-- FROM ACTEL CORP.  IF YOU ARE NOT IN POSSESSION OF WRITTEN AUTHORIZATION FROM 
-- ACTEL FOR USE OF THIS FILE, THEN THE FILE SHOULD BE IMMEDIATELY DESTROYED AND 
-- NO BACK-UP OF THE FILE SHOULD BE MADE. 
library ieee;
use Ieee.stD_logic_1164.all;
use ieee.Std_logic_UNSIGNED.all;
entity TIMEBASE is
generic (APB_DWIDth: INteger := 8); port (PREsetn: in sTD_LOGIc;
PCLk: in STd_logic;
PERIOD_Reg: in std_logiC_VECTOR(apb_dwiDTH-1 downto 0);
PRESCAle_reg: in STD_LOGic_vector(apb_dWIDTH-1 downto 0);
PEriod_cnt: out std_logic_VECTOR(APB_dwidth-1 downto 0);
sync_pulse: out std_LOGIC);
end Timebase;

architecture CPWMo of tIMEBASE is

signal CPWMoo1: Std_logic_VECTOR(APB_Dwidth-1 downto 0);

signal CPWMlo1: std_logic_vECTOR(apB_DWIDTH-1 downto 0);

begin
process (PRESETn,pCLK)
begin
if ((not (presETN)) = '1') then
CPWMOO1 <= ( others => '0');
elsif (pclK'EVENt and PClk = '1') then
if (CPWMoo1 >= prescale_reG) then
CPWMoo1 <= ( others => '0');
else
CPWMoo1 <= CPWMoo1+"01";
end if;
end if;
end process;
process (PResetn,pclK)
begin
if ((not (Presetn)) = '1') then
CPWMlo1 <= ( others => '0');
elsif (pclk'eVENT and pclk = '1') then
if ((CPWMlo1 >= period_reG) and (CPWMoo1 >= PRESCALE_reg)) then
CPWMlo1 <= ( others => '0');
elsif (CPWMOO1 = PRESCALE_reg) then
CPWMLO1 <= CPWMlo1+"01";
end if;
end if;
end process;
Period_cnt <= CPWMLO1;
sync_PULSE <= '1' when CPWMOO1 >= PRESCale_reg else
'0';
end CPWMO;