testbench.vhd

来自「Actel Fusion System Management Developme」· VHDL 代码 · 共 71 行

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-- Created by Actel SmartDesign Tue Mar 17 15:29:25 2009
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library ieee;
use ieee.std_logic_1164.all;

entity testbench is
end testbench;

architecture behavioral of testbench is

    constant SYSCLK_PERIOD : time := 100 ns;

    signal SYSCLK : std_logic := '0';
    signal NSYSRESET : std_logic := '0';

    component ABC
        -- ports
        port( 
            -- Inputs
            NSYSRESET : in std_logic;
            RX : in std_logic;
            SYSCLK : in std_logic;

            -- Outputs
            TX : out std_logic

            -- Inouts

        );
    end component;

begin

    process
        variable vhdl_initial : BOOLEAN := TRUE;

    begin
        if ( vhdl_initial ) then
            -- Assert Reset
            NSYSRESET <= '0';
            wait for ( SYSCLK_PERIOD * 10 );
            
            NSYSRESET <= '1';
            wait;
        end if;
    end process;

    -- 10MHz Clock Driver
    SYSCLK <= not SYSCLK after (SYSCLK_PERIOD / 2);

    -- Instantiate Unit Under Test:  ABC
    ABC_0 : ABC
        -- port map
        port map( 
            -- Inputs
            NSYSRESET => NSYSRESET,
            RX => '0',
            SYSCLK => SYSCLK,

            -- Outputs
            TX =>  open

            -- Inouts

        );

end behavioral;