abc.vhd

Actel Fusion System Management Development Kit UART Example. Contains Libero design using CoreABC. P

-- Version: 8.5 SP1 8.5.1.13

library ieee;
use ieee.std_logic_1164.all;
library fusion;
use fusion.all;
library COREUARTAPB_LIB;
use COREUARTAPB_LIB.all;

entity ABC is

    port( NSYSRESET : in    std_logic;
          RX        : in    std_logic;
          SYSCLK    : in    std_logic;
          TX        : out   std_logic
        );

end ABC;

architecture DEF_ARCH of ABC is 

  component KELLO
    port( POWERDOWN : in    std_logic := 'U';
          CLKA      : in    std_logic := 'U';
          LOCK      : out   std_logic;
          GLA       : out   std_logic;
          OADIVRST  : in    std_logic := 'U'
        );
  end component;

  component CoreAPB
    generic (ApbSlot0Enable:integer := 0; 
        ApbSlot10Enable:integer := 0; 
        ApbSlot11Enable:integer := 0; 
        ApbSlot12Enable:integer := 0; 
        ApbSlot13Enable:integer := 0; 
        ApbSlot14Enable:integer := 0; 
        ApbSlot15Enable:integer := 0; ApbSlot1Enable:integer := 0; 
        ApbSlot2Enable:integer := 0; ApbSlot3Enable:integer := 0; 
        ApbSlot4Enable:integer := 0; ApbSlot5Enable:integer := 0; 
        ApbSlot6Enable:integer := 0; ApbSlot7Enable:integer := 0; 
        ApbSlot8Enable:integer := 0; ApbSlot9Enable:integer := 0
        );

    port( PWRITE    : in    std_logic := 'U';
          PENABLE   : in    std_logic := 'U';
          PWRITES   : out   std_logic;
          PENABLES  : out   std_logic;
          PSELS0    : out   std_logic;
          PSELS1    : out   std_logic;
          PSELS2    : out   std_logic;
          PSELS3    : out   std_logic;
          PSELS4    : out   std_logic;
          PSELS5    : out   std_logic;
          PSELS6    : out   std_logic;
          PSELS7    : out   std_logic;
          PSELS8    : out   std_logic;
          PSELS9    : out   std_logic;
          PSELS10   : out   std_logic;
          PSELS11   : out   std_logic;
          PSELS12   : out   std_logic;
          PSELS13   : out   std_logic;
          PSELS14   : out   std_logic;
          PSELS15   : out   std_logic;
          PADDR     : in    std_logic_vector(23 downto 0) := (others => 'U');
          PWDATA    : in    std_logic_vector(31 downto 0) := (others => 'U');
          PRDATA    : out   std_logic_vector(31 downto 0);
          PSELECT   : in    std_logic_vector(15 downto 0) := (others => 'U');
          PADDRS    : out   std_logic_vector(23 downto 0);
          PWDATAS   : out   std_logic_vector(31 downto 0);
          PRDATAS0  : in    std_logic_vector(31 downto 0) := (others => 'U');
          PRDATAS1  : in    std_logic_vector(31 downto 0) := (others => 'U');
          PRDATAS2  : in    std_logic_vector(31 downto 0) := (others => 'U');
          PRDATAS3  : in    std_logic_vector(31 downto 0) := (others => 'U');
          PRDATAS4  : in    std_logic_vector(31 downto 0) := (others => 'U');
          PRDATAS5  : in    std_logic_vector(31 downto 0) := (others => 'U');
          PRDATAS6  : in    std_logic_vector(31 downto 0) := (others => 'U');
          PRDATAS7  : in    std_logic_vector(31 downto 0) := (others => 'U');
          PRDATAS8  : in    std_logic_vector(31 downto 0) := (others => 'U');
          PRDATAS9  : in    std_logic_vector(31 downto 0) := (others => 'U');
          PRDATAS10 : in    std_logic_vector(31 downto 0) := (others => 'U');
          PRDATAS11 : in    std_logic_vector(31 downto 0) := (others => 'U');
          PRDATAS12 : in    std_logic_vector(31 downto 0) := (others => 'U');
          PRDATAS13 : in    std_logic_vector(31 downto 0) := (others => 'U');
          PRDATAS14 : in    std_logic_vector(31 downto 0) := (others => 'U');
          PRDATAS15 : in    std_logic_vector(31 downto 0) := (others => 'U')
        );
  end component;

  component ABCD
    port( INTACT                : out   std_logic;
          INTREQ                : in    std_logic := 'U';
          NSYSRESET             : in    std_logic := 'U';
          PCLK                  : in    std_logic := 'U';
          PREADY                : in    std_logic := 'U';
          PRESETN               : out   std_logic;
          APBmaster_PENABLE     : out   std_logic;
          APBmaster_PWRITE      : out   std_logic;
          InitConfig_INITDATVAL : in    std_logic := 'U';
          InitConfig_INITDONE   : in    std_logic := 'U';
          IO_IN                 : in    std_logic_vector(3 downto 0) := (others => 'U');
          IO_OUT                : out   std_logic_vector(3 downto 0);
          APBmaster_PADDR       : out   std_logic_vector(7 downto 0);
          APBmaster_PRDATA      : in    std_logic_vector(15 downto 0) := (others => 'U');
          APBmaster_PSELECT     : out   std_logic_vector(15 downto 0);
          APBmaster_PWDATA      : out   std_logic_vector(15 downto 0);
          InitConfig_INITADDR   : in    std_logic_vector(10 downto 0) := (others => 'U');
          InitConfig_INITDATA   : in    std_logic_vector(8 downto 0) := (others => 'U')
        );
  end component;

  component VCC
    port( Y : out   std_logic
        );
  end component;

  component INBUF_LVCMOS33
    port( PAD : in    std_logic := 'U';
          Y   : out   std_logic
        );
  end component;

  component GND
    port( Y : out   std_logic
        );
  end component;

  component CoreUARTapb
    generic (BAUD_VALUE:integer := 0; FAMILY:integer := 0; 
        FIXEDMODE:integer := 0; PRG_BIT8:integer := 0; 
        PRG_PARITY:integer := 0; RX_FIFO:integer := 0; 
        TX_FIFO:integer := 0);

    port( OVERFLOW   : out   std_logic;
          PARITY_ERR : out   std_logic;
          PCLK       : in    std_logic := 'U';
          PENABLE    : in    std_logic := 'U';
          PRESETN    : in    std_logic := 'U';
          PSEL       : in    std_logic := 'U';
          PWRITE     : in    std_logic := 'U';
          RX         : in    std_logic := 'U';
          RXRDY      : out   std_logic;
          TX         : out   std_logic;
          TXRDY      : out   std_logic;
          PADDR      : in    std_logic_vector(4 downto 2) := (others => 'U');
          PRDATA     : out   std_logic_vector(7 downto 0);
          PWDATA     : in    std_logic_vector(7 downto 0) := (others => 'U')
        );
  end component;

    signal \ABCD_0_APBmaster_PADDR_[0]\, 
        \ABCD_0_APBmaster_PADDR_[1]\, 
        \ABCD_0_APBmaster_PADDR_[2]\, 
        \ABCD_0_APBmaster_PADDR_[3]\, 
        \ABCD_0_APBmaster_PADDR_[4]\, 
        \ABCD_0_APBmaster_PADDR_[5]\, 
        \ABCD_0_APBmaster_PADDR_[6]\, 
        \ABCD_0_APBmaster_PADDR_[7]\, ABCD_0_APBmaster_PENABLE, 
        \ABCD_0_APBmaster_PRDATA_[0]\, 
        \ABCD_0_APBmaster_PRDATA_[1]\, 
        \ABCD_0_APBmaster_PRDATA_[2]\, 
        \ABCD_0_APBmaster_PRDATA_[3]\, 
        \ABCD_0_APBmaster_PRDATA_[4]\, 
        \ABCD_0_APBmaster_PRDATA_[5]\, 
        \ABCD_0_APBmaster_PRDATA_[6]\, 
        \ABCD_0_APBmaster_PRDATA_[7]\, 
        \ABCD_0_APBmaster_PRDATA_[8]\, 
        \ABCD_0_APBmaster_PRDATA_[9]\, 
        \ABCD_0_APBmaster_PRDATA_[10]\, 
        \ABCD_0_APBmaster_PRDATA_[11]\, 
        \ABCD_0_APBmaster_PRDATA_[12]\, 
        \ABCD_0_APBmaster_PRDATA_[13]\, 
        \ABCD_0_APBmaster_PRDATA_[14]\, 
        \ABCD_0_APBmaster_PRDATA_[15]\, 
        \ABCD_0_APBmaster_PRDATA_[16]\, 
        \ABCD_0_APBmaster_PRDATA_[17]\, 
        \ABCD_0_APBmaster_PRDATA_[18]\, 
        \ABCD_0_APBmaster_PRDATA_[19]\, 
        \ABCD_0_APBmaster_PRDATA_[20]\, 
        \ABCD_0_APBmaster_PRDATA_[21]\, 
        \ABCD_0_APBmaster_PRDATA_[22]\, 
        \ABCD_0_APBmaster_PRDATA_[23]\, 
        \ABCD_0_APBmaster_PRDATA_[24]\, 
        \ABCD_0_APBmaster_PRDATA_[25]\, 
        \ABCD_0_APBmaster_PRDATA_[26]\, 
        \ABCD_0_APBmaster_PRDATA_[27]\, 
        \ABCD_0_APBmaster_PRDATA_[28]\, 
        \ABCD_0_APBmaster_PRDATA_[29]\, 
        \ABCD_0_APBmaster_PRDATA_[30]\, 
        \ABCD_0_APBmaster_PRDATA_[31]\, 
        \ABCD_0_APBmaster_PSELx_[0]\, 
        \ABCD_0_APBmaster_PSELx_[1]\, 
        \ABCD_0_APBmaster_PSELx_[2]\, 
        \ABCD_0_APBmaster_PSELx_[3]\, 
        \ABCD_0_APBmaster_PSELx_[4]\, 
        \ABCD_0_APBmaster_PSELx_[5]\, 
        \ABCD_0_APBmaster_PSELx_[6]\, 
        \ABCD_0_APBmaster_PSELx_[7]\, 
        \ABCD_0_APBmaster_PSELx_[8]\, 
        \ABCD_0_APBmaster_PSELx_[9]\, 
        \ABCD_0_APBmaster_PSELx_[10]\, 
        \ABCD_0_APBmaster_PSELx_[11]\, 
        \ABCD_0_APBmaster_PSELx_[12]\, 
        \ABCD_0_APBmaster_PSELx_[13]\, 
        \ABCD_0_APBmaster_PSELx_[14]\, 
        \ABCD_0_APBmaster_PSELx_[15]\, 
        \ABCD_0_APBmaster_PWDATA_[0]\, 
        \ABCD_0_APBmaster_PWDATA_[1]\, 
        \ABCD_0_APBmaster_PWDATA_[2]\, 
        \ABCD_0_APBmaster_PWDATA_[3]\, 
        \ABCD_0_APBmaster_PWDATA_[4]\, 
        \ABCD_0_APBmaster_PWDATA_[5]\, 
        \ABCD_0_APBmaster_PWDATA_[6]\, 
        \ABCD_0_APBmaster_PWDATA_[7]\, 
        \ABCD_0_APBmaster_PWDATA_[8]\, 
        \ABCD_0_APBmaster_PWDATA_[9]\, 
        \ABCD_0_APBmaster_PWDATA_[10]\, 
        \ABCD_0_APBmaster_PWDATA_[11]\, 
        \ABCD_0_APBmaster_PWDATA_[12]\, 
        \ABCD_0_APBmaster_PWDATA_[13]\, 
        \ABCD_0_APBmaster_PWDATA_[14]\, 
        \ABCD_0_APBmaster_PWDATA_[15]\, ABCD_0_APBmaster_PWRITE, 
        ABCD_0_PRESETN, \CoreAPB_0_APBmslave0_PADDR_[0]\, 
        \CoreAPB_0_APBmslave0_PADDR_[1]\, 
        \CoreAPB_0_APBmslave0_PADDR_[2]\, 
        \CoreAPB_0_APBmslave0_PADDR_[3]\, 
        \CoreAPB_0_APBmslave0_PADDR_[4]\, 
        \CoreAPB_0_APBmslave0_PADDR_[5]\, 
        \CoreAPB_0_APBmslave0_PADDR_[6]\, 
        \CoreAPB_0_APBmslave0_PADDR_[7]\, 
        \CoreAPB_0_APBmslave0_PADDR_[8]\, 
        \CoreAPB_0_APBmslave0_PADDR_[9]\, 
        \CoreAPB_0_APBmslave0_PADDR_[10]\, 
        \CoreAPB_0_APBmslave0_PADDR_[11]\, 
        \CoreAPB_0_APBmslave0_PADDR_[12]\, 
        \CoreAPB_0_APBmslave0_PADDR_[13]\, 
        \CoreAPB_0_APBmslave0_PADDR_[14]\, 
        \CoreAPB_0_APBmslave0_PADDR_[15]\, 
        \CoreAPB_0_APBmslave0_PADDR_[16]\, 
        \CoreAPB_0_APBmslave0_PADDR_[17]\, 
        \CoreAPB_0_APBmslave0_PADDR_[18]\, 
        \CoreAPB_0_APBmslave0_PADDR_[19]\, 
        \CoreAPB_0_APBmslave0_PADDR_[20]\, 
        \CoreAPB_0_APBmslave0_PADDR_[21]\, 
        \CoreAPB_0_APBmslave0_PADDR_[22]\, 
        \CoreAPB_0_APBmslave0_PADDR_[23]\, 
        CoreAPB_0_APBmslave0_PENABLE, 
        \CoreAPB_0_APBmslave0_PRDATA_[0]\, 
        \CoreAPB_0_APBmslave0_PRDATA_[1]\, 
        \CoreAPB_0_APBmslave0_PRDATA_[2]\, 
        \CoreAPB_0_APBmslave0_PRDATA_[3]\, 
        \CoreAPB_0_APBmslave0_PRDATA_[4]\, 
        \CoreAPB_0_APBmslave0_PRDATA_[5]\, 
        \CoreAPB_0_APBmslave0_PRDATA_[6]\, 
        \CoreAPB_0_APBmslave0_PRDATA_[7]\, 
        CoreAPB_0_APBmslave0_PSELx, 
        \CoreAPB_0_APBmslave0_PWDATA_[0]\, 
        \CoreAPB_0_APBmslave0_PWDATA_[1]\, 
        \CoreAPB_0_APBmslave0_PWDATA_[2]\, 
        \CoreAPB_0_APBmslave0_PWDATA_[3]\, 
        \CoreAPB_0_APBmslave0_PWDATA_[4]\, 
        \CoreAPB_0_APBmslave0_PWDATA_[5]\, 
        \CoreAPB_0_APBmslave0_PWDATA_[6]\, 
        \CoreAPB_0_APBmslave0_PWDATA_[7]\, 
        \CoreAPB_0_APBmslave0_PWDATA_[8]\, 
        \CoreAPB_0_APBmslave0_PWDATA_[9]\, 
        \CoreAPB_0_APBmslave0_PWDATA_[10]\, 
        \CoreAPB_0_APBmslave0_PWDATA_[11]\, 
        \CoreAPB_0_APBmslave0_PWDATA_[12]\, 
        \CoreAPB_0_APBmslave0_PWDATA_[13]\, 
        \CoreAPB_0_APBmslave0_PWDATA_[14]\, 
        \CoreAPB_0_APBmslave0_PWDATA_[15]\, 
        \CoreAPB_0_APBmslave0_PWDATA_[16]\, 
        \CoreAPB_0_APBmslave0_PWDATA_[17]\, 
        \CoreAPB_0_APBmslave0_PWDATA_[18]\, 
        \CoreAPB_0_APBmslave0_PWDATA_[19]\, 
        \CoreAPB_0_APBmslave0_PWDATA_[20]\, 
        \CoreAPB_0_APBmslave0_PWDATA_[21]\, 
        \CoreAPB_0_APBmslave0_PWDATA_[22]\, 
        \CoreAPB_0_APBmslave0_PWDATA_[23]\, 
        \CoreAPB_0_APBmslave0_PWDATA_[24]\,