smtr.vhd

Actel Fusion System Management Development Kit UART Example. Contains Libero design using CoreABC. P

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-- (c) Copyright 2006 Actel Corporation
--
-- name:		smtr.vhd
-- function:	System Monitor State Machine (Transition Phase) block
-- Rev:			1.2 28Apr06
--
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library ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;entity
ccfdxrhchsz is generic(qjnhkksszkf:integer:=0;hbgvpqcgtwm:integer:=0;
fnscgtbnskd:integer:=1;xkcbxcnxxhg:integer:=9;cvczfvkpmqh:integer:=9;
dgswbvgbtfw:integer:=0);port(jktbwpsfwwq:in std_logic;gfrqwfndskc:in std_logic;
kpffvbpxmsf:in std_logic_vector(4 downto 0);txjjszxznxd:in std_logic;
zszmcgpbgkw:out std_logic;dmrgcpvxzhk:out std_logic;svfntzchvmh:in
std_logic_vector((((2**qjnhkksszkf)*32)-1)downto 0);nvpcwbhffsn:out
std_logic_vector((((2**hbgvpqcgtwm)*32)-1)downto 0);rthvrwwpqpk:in
std_logic_vector(cvczfvkpmqh-1 downto 0);rbvjpdddhcz:in std_logic;
xtfkmfbzksq:in std_logic_vector(8 downto 0);hgtrcfcxkrb:in std_logic;
qbrqxpmkpsw:in std_logic_vector(cvczfvkpmqh-1 downto 0);nktsnhmjrbx:in
std_logic;rbkmxbvpcdx:out std_logic;zngtgckbfnx:out std_logic_vector(
xkcbxcnxxhg-1 downto 0);mpnqskgzxzf:out std_logic;qxzrwpjhcww:in
std_logic_vector(8 downto 0);dnmrkvrtbjn:in std_logic;kxzjqrqjbxm:out
std_logic_vector(cvczfvkpmqh-1 downto 0);ngrmnspbvxf:out std_logic;
hxqsbsdhfvm:out std_logic;mvbwzprdfrk:out std_logic_vector(8 downto 0);
dtdngjrdwms:out std_logic_vector(cvczfvkpmqh-1 downto 0);ndngwnmwgbm:out
std_logic;svpbmqwvncp:out std_logic;jfkkdmfhcdn:out std_logic_vector(8 downto 0)
;tpxkpvnpvvn:in std_logic_vector(8 downto 0);xgnmbzmtzbb:out std_logic);end
ccfdxrhchsz;architecture djzfpsxghmt of ccfdxrhchsz is constant
twqmbkvsqjv:std_logic_vector(3 downto 0):="0010";constant
ffskdxgczkf:std_logic_vector(3 downto 0):="0011";constant
jwgwqvwgzqc:std_logic_vector(3 downto 0):="0100";constant
hdmrhsdqkpf:std_logic_vector(3 downto 0):="0101";constant
vfhwbpmxnhg:std_logic_vector(3 downto 0):="0110";constant
hjsptcsxwwj:std_logic_vector(3 downto 0):="0111";constant
qkfdnddgfnr:std_logic_vector(3 downto 0):="1000";constant
hvdtwfkzgjf:std_logic_vector(3 downto 0):="1001";constant
tgmgxbkhgvv:std_logic_vector(3 downto 0):="1010";constant
mrkkbfgjnsm:std_logic_vector(3 downto 0):="1011";constant
fqsggvsnbpw:std_logic_vector(3 downto 0):="1100";constant
vkzrtdvqxtm:std_logic_vector(3 downto 0):="1101";constant
cprxxpgqtzv:std_logic_vector(3 downto 0):="1110";constant
bzfzwfqrsfh:std_logic_vector(3 downto 0):="1111";constant
gwcnpmdcdgf:std_logic_vector(1 downto 0):="00";constant
cxqfrrsmjms:std_logic_vector(1 downto 0):="01";constant
scfrdfnbqsw:std_logic_vector(1 downto 0):="10";signal djmcnprrmvb:std_logic;
signal hpqvbfpswtk:std_logic;signal phrnkhgdbnj:std_logic_vector(4 downto 0);
signal wjpccrvpdms:std_logic;signal zzhpvrjsvfq:std_logic;signal
xdjpqrrmkhk:std_logic;signal fzffhdchtwx:std_logic_vector((((2**qjnhkksszkf)*32)
-1)downto 0);signal fjxrvdqhdqm:std_logic_vector((((2**hbgvpqcgtwm)*32)-1)
downto 0);signal fctrrrgrnzt:std_logic_vector(cvczfvkpmqh-1 downto 0);signal
qgpxkqfdsgs:std_logic;signal wkjnqmhbcwj:std_logic_vector(8 downto 0);signal
sppmwdzsssj:std_logic;signal kftcmqgpwdb:std_logic_vector(cvczfvkpmqh-1 downto
0);signal swwxrvfdnmg:std_logic;signal jzsfkrwzvsw:std_logic;signal
tvtbbxkbhjr:std_logic_vector(xkcbxcnxxhg-1 downto 0);signal
hcrjtrhwvbj:std_logic;signal zgnrsfkdbqw:std_logic_vector(8 downto 0);signal
zdbgxnzghqv:std_logic;signal svfszvvwxqd:std_logic_vector(cvczfvkpmqh-1 downto
0);signal cnwzzrhdsqv:std_logic;signal fgbkzdqjprd:std_logic;signal
qwfrxhqbhft:std_logic_vector(8 downto 0);signal vkmkdwnprxg:std_logic_vector(
cvczfvkpmqh-1 downto 0);signal smjmfvmgvmf:std_logic;signal
bqhmpqxgttc:std_logic;signal gbxmbbjwptj:std_logic_vector(8 downto 0);signal
thsjqmjnffp:std_logic_vector(8 downto 0);signal bppqndbbfvm:std_logic;type
bzhvcjnmprc is(tddtwhmsmxw,csrjrbfvktn,vrqwnsvfhbf,tcngxxfgmdg,vwzxznxmxjj,
bfsztxmjbwz,ncvfznsdsmv,nksjwxsrvfg,jhdgkzrksxb,mxpxttqxdhv,whzkgttntpq,
pgtwqqmcgdx);signal frcskdnwvmx:bzhvcjnmprc;signal pstdkkzgbgr:bzhvcjnmprc;
signal hqmqdkzbnrr:std_logic;signal fjznqcrvpff:std_logic_vector(xkcbxcnxxhg-1
downto 0);signal strbgbnthfj:std_logic_vector(1 downto 0);signal
whzfpthqmgz:std_logic_vector(1 downto 0);signal rjhhzsggrtr:std_logic_vector(8
downto 0);signal xgnxxpdktqq:std_logic_vector(8 downto 0);signal
zfgtfxdvzvc:std_logic;signal hjwgppzxqgk:std_logic;signal cvjkzwfgfxd:std_logic;
signal nfzjqqfddbb:std_logic;signal bjhvcvnjcsg:std_logic_vector(8 downto 0);
signal fkjmfwsgfmv:std_logic_vector(3 downto 0);signal
jjnnjkrjzfq:std_logic_vector(cvczfvkpmqh-1 downto 0);signal
qsmttxbhpgn:std_logic_vector(cvczfvkpmqh-1 downto 0);signal
nqhzsnspnjx:std_logic_vector(1 downto 0);signal vxwrrdhrwzp:std_logic;signal
qgnzcpmbksd:std_logic_vector(8 downto 0);signal vdsdnrcxgvw:std_logic_vector(8
downto 0);signal drwrxhmtwrc:std_logic_vector(8 downto 0);signal
mgqspspvvwp:std_logic_vector(8 downto 0);signal zzcdvnbsprb:std_logic;signal
xmqhrfdbnvv:std_logic;signal fwwttwfqzbg:std_logic_vector(1 downto 0);signal
mwwwwqsdrms:std_logic_vector(1 downto 0);signal gjdrndrcvkr:std_logic;signal
jvxfmjbzjmc:std_logic;signal gbzdgjmckpp:std_logic;signal hfnznbmwdbg:std_logic;
signal zsmmssvkxrp:std_logic_vector(4 downto 0);signal
rzhvxzjzccf:std_logic_vector(4 downto 0);signal pwgctrqbjqq:std_logic;signal
tcjcfmnswmq:std_logic_vector(4 downto 0);signal fsztzzhdhbt:std_logic_vector(4
downto 0);signal zrwhskvshjw:std_logic;signal cvpkmgjqwzb:std_logic;signal
mwzbqqvzwjt:std_logic_vector((((2**hbgvpqcgtwm)*32)-1)downto 0);signal
rrghpjvpszt:std_logic_vector(4 downto 0);signal czjszchcxth:std_logic;signal
prtrmdfzspn:std_logic_vector(4 downto 0);signal zsxdfhnrkrg:std_logic;signal
tbbdzwmpmht:std_logic;signal pwsmjbnvbmm:std_logic;signal
bpjpvnnvzdm:std_logic_vector(7 downto 0);signal spxmmvzpxxs:std_logic_vector(1
downto 0);signal rhjxdmgzftc:std_logic_vector(1 downto 0);signal
dxqdbrvdqqj:std_logic;signal rdqhbcjchvq:std_logic;signal
zzrhmbvmjcf:std_logic_vector(1 downto 0);signal znjtscvsvcs:std_logic;signal
hnbsspwxkpd:std_logic;signal dttrrgvsnmg:std_logic;signal jnfrmfqggmk:std_logic;
signal mpdmwvwvmgs:std_logic;signal qfgwvhsgqst:std_logic;signal
vgdscntczht:std_logic;signal vmpskspphnb:std_logic;signal rxhtxbbkhjf:std_logic;
signal sxrhkdkngbh:std_logic;signal zzkqpqxsjxx:std_logic;signal
dvqzjxhqhrh:std_logic;signal rhzdqmbwsdd:std_logic;signal zcmhpccwtzh:std_logic;
signal bnxqxhthfkm:std_logic;signal xvghwqhtwrc:std_logic;signal
ffqqvqhktvc:std_logic;signal fjsjhgxtkfv:std_logic;signal xjrbtnwdszs:std_logic;
signal fdwkpqztzkr:std_logic;signal gxkgtngfhqr:std_logic;signal
cpwfrthtnfr:std_logic;signal xqshddsxjxq:std_logic;signal thrxvbszptn:std_logic;
signal zzzxtvvjqhf:std_logic;signal nwjvqqsgrjz:std_logic;constant
nhjqdsptgfp:std_logic_vector(8 downto 0):="111111111";constant
gwmqzbkfvkx:std_logic_vector(6 downto 0):="0000000";begin
fkjmfwsgfmv<=thsjqmjnffp(8 downto 5);fwwttwfqzbg<=thsjqmjnffp(1 downto 0);
rrghpjvpszt<=thsjqmjnffp(4 downto 0);prtrmdfzspn<=thsjqmjnffp(4 downto 0);
zsmmssvkxrp<=thsjqmjnffp(4 downto 0);tcjcfmnswmq<=thsjqmjnffp(4 downto 0);
spxmmvzpxxs<=thsjqmjnffp(1 downto 0);bpjpvnnvzdm<=thsjqmjnffp(7 downto 0);
zzkqpqxsjxx<=thsjqmjnffp(4);whzfpthqmgz<=thsjqmjnffp(1 downto 0);
xgnxxpdktqq<=thsjqmjnffp(8 downto 0);zzrhmbvmjcf<=thsjqmjnffp(1 downto 0);
process(djmcnprrmvb,hpqvbfpswtk)begin if hpqvbfpswtk='0' then rhjxdmgzftc<=(
others=>'0');elsif rising_edge(djmcnprrmvb)then if dxqdbrvdqqj='1' then
rhjxdmgzftc<=spxmmvzpxxs;end if;end if;end process;dtqpjwspznp:if qjnhkksszkf=0
generate rzhvxzjzccf<=(others=>'0');cvpkmgjqwzb<=fzffhdchtwx(to_integer(
unsigned(rrghpjvpszt)));end generate;mmjxzzpzvzj:if qjnhkksszkf>0 generate
process(djmcnprrmvb,hpqvbfpswtk)begin if hpqvbfpswtk='0' then rzhvxzjzccf<=(
others=>'0');elsif rising_edge(djmcnprrmvb)then if pwgctrqbjqq='1' then
rzhvxzjzccf<=zsmmssvkxrp;end if;end if;end process;cvpkmgjqwzb<=fzffhdchtwx(((
to_integer(unsigned(rzhvxzjzccf(qjnhkksszkf-1 downto 0))))*32)+(to_integer(
unsigned(rrghpjvpszt))));end generate;fmjpnrkwjrc:if hbgvpqcgtwm=0 generate
fsztzzhdhbt<=(others=>'0');vsfzgsfwgdd:process(djmcnprrmvb,hpqvbfpswtk)variable
bpkzfmkvkrj:integer range 0 to 3;variable bvjxfbhxgkj:integer range 0 to 31;
begin bpkzfmkvkrj:=0;bvjxfbhxgkj:=0;if hpqvbfpswtk='0' then mwzbqqvzwjt<=(
others=>'0');elsif rising_edge(djmcnprrmvb)then bpkzfmkvkrj:=(to_integer(
unsigned(rhjxdmgzftc)));bvjxfbhxgkj:=(to_integer(unsigned(prtrmdfzspn)));if
pwsmjbnvbmm='1' then mwzbqqvzwjt((bpkzfmkvkrj*8)+7)<=bpjpvnnvzdm(7);mwzbqqvzwjt(
(bpkzfmkvkrj*8)+6)<=bpjpvnnvzdm(6);mwzbqqvzwjt((bpkzfmkvkrj*8)+5)<=bpjpvnnvzdm(
5);mwzbqqvzwjt((bpkzfmkvkrj*8)+4)<=bpjpvnnvzdm(4);mwzbqqvzwjt((bpkzfmkvkrj*8)+3)
<=bpjpvnnvzdm(3);mwzbqqvzwjt((bpkzfmkvkrj*8)+2)<=bpjpvnnvzdm(2);mwzbqqvzwjt((
bpkzfmkvkrj*8)+1)<=bpjpvnnvzdm(1);mwzbqqvzwjt((bpkzfmkvkrj*8)+0)<=bpjpvnnvzdm(0)
;elsif zsxdfhnrkrg='1' then mwzbqqvzwjt(bvjxfbhxgkj)<='1';elsif tbbdzwmpmht='1'
then mwzbqqvzwjt(bvjxfbhxgkj)<='0';end if;end if;end process vsfzgsfwgdd;end
generate;rknpnmhwmhk:if hbgvpqcgtwm>0 generate process(djmcnprrmvb,hpqvbfpswtk)
begin if hpqvbfpswtk='0' then fsztzzhdhbt<=(others=>'0');elsif rising_edge(
djmcnprrmvb)then if zrwhskvshjw='1' then fsztzzhdhbt<=tcjcfmnswmq;end if;end if;
end process;ssvkkjmxdmx:process(djmcnprrmvb,hpqvbfpswtk)variable
nxgzktkpjgj:unsigned(hbgvpqcgtwm-1 downto 0);variable bpkzfmkvkrj:integer range
0 to 3;variable bvjxfbhxgkj:integer range 0 to 31;begin if hpqvbfpswtk='0' then
mwzbqqvzwjt<=(others=>'0');elsif rising_edge(djmcnprrmvb)then
nxgzktkpjgj:=unsigned(fsztzzhdhbt(hbgvpqcgtwm-1 downto 0));bpkzfmkvkrj:=(
to_integer(unsigned(rhjxdmgzftc)));bvjxfbhxgkj:=(to_integer(unsigned(
prtrmdfzspn)));if pwsmjbnvbmm='1' then mwzbqqvzwjt((to_integer(nxgzktkpjgj)*32)
+(bpkzfmkvkrj*8)+7)<=bpjpvnnvzdm(7);mwzbqqvzwjt((to_integer(nxgzktkpjgj)*32)+(
bpkzfmkvkrj*8)+6)<=bpjpvnnvzdm(6);mwzbqqvzwjt((to_integer(nxgzktkpjgj)*32)+(
bpkzfmkvkrj*8)+5)<=bpjpvnnvzdm(5);mwzbqqvzwjt((to_integer(nxgzktkpjgj)*32)+(
bpkzfmkvkrj*8)+4)<=bpjpvnnvzdm(4);mwzbqqvzwjt((to_integer(nxgzktkpjgj)*32)+(
bpkzfmkvkrj*8)+3)<=bpjpvnnvzdm(3);mwzbqqvzwjt((to_integer(nxgzktkpjgj)*32)+(
bpkzfmkvkrj*8)+2)<=bpjpvnnvzdm(2);mwzbqqvzwjt((to_integer(nxgzktkpjgj)*32)+(
bpkzfmkvkrj*8)+1)<=bpjpvnnvzdm(1);mwzbqqvzwjt((to_integer(nxgzktkpjgj)*32)+(
bpkzfmkvkrj*8)+0)<=bpjpvnnvzdm(0);elsif zsxdfhnrkrg='1' then mwzbqqvzwjt((
to_integer(nxgzktkpjgj)*32)+bvjxfbhxgkj)<='1';elsif tbbdzwmpmht='1' then
mwzbqqvzwjt((to_integer(nxgzktkpjgj)*32)+bvjxfbhxgkj)<='0';end if;end if;end
process ssvkkjmxdmx;end generate;process(djmcnprrmvb,hpqvbfpswtk)begin if
hpqvbfpswtk='0' then dvqzjxhqhrh<='0';elsif rising_edge(djmcnprrmvb)then if
rhzdqmbwsdd='1' then dvqzjxhqhrh<=zzkqpqxsjxx;end if;end if;end process;
qgtkpxrgqqs:process(hnbsspwxkpd,zcmhpccwtzh,zgnrsfkdbqw,bnxqxhthfkm,mpdmwvwvmgs,
xvghwqhtwrc,qfgwvhsgqst,ffqqvqhktvc,rxhtxbbkhjf,fjsjhgxtkfv,jnfrmfqggmk)
variable prcfwhmwpff:std_logic_vector(4 downto 0);begin
prcfwhmwpff:=fjsjhgxtkfv&ffqqvqhktvc&xvghwqhtwrc&bnxqxhthfkm&zcmhpccwtzh;case
prcfwhmwpff is when "00001"=>znjtscvsvcs<=zgnrsfkdbqw(0);when
"00010"=>znjtscvsvcs<=mpdmwvwvmgs;when "00100"=>znjtscvsvcs<=qfgwvhsgqst;when
"01000"=>znjtscvsvcs<=rxhtxbbkhjf;when "10000"=>znjtscvsvcs<=jnfrmfqggmk;when
others=>znjtscvsvcs<=hnbsspwxkpd;end case;end process qgtkpxrgqqs;process(
djmcnprrmvb,hpqvbfpswtk)begin if hpqvbfpswtk='0' then hnbsspwxkpd<='0';elsif
rising_edge(djmcnprrmvb)then hnbsspwxkpd<=znjtscvsvcs;end if;end process;
vnjtgtptszx:process(jnfrmfqggmk,xjrbtnwdszs,zgnrsfkdbqw,fdwkpqztzkr,vgdscntczht,