initcfg_xf.vhd

Actel Fusion System Management Development Kit UART Example. Contains Libero design using CoreABC. P

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-- (c) Copyright 2005 Actel Corporation
--
-- name:		initcfg_xf.vhd
-- function:	SMARTgen IP
-- Rev:			1.4 28Nov05
--
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library ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;entity
jhmkpjjmdkx is port(bgcgxskznzs:in std_logic;smvsxpgjmjj:in std_logic;
pbrmgfnrnxq:in std_logic;mrjgbfsqxpv:in std_logic;bmwnqmctdkc:in std_logic;
pprvvcxpxrw:in std_logic;ptbgdzqpfjh:in std_logic;zkngqtzrgks:in std_logic;
mzbhqpgcrqx:in std_logic;rntfrjgxqfn:out std_logic;jdcjstkrfpq:out std_logic;
nnrhkdmqgrk:out std_logic;vqxxxfhknzt:out std_logic;tkbnpjzqwmx:out std_logic);
end jhmkpjjmdkx;architecture bmnqpbgpmvq of jhmkpjjmdkx is signal
zmbsbbtjszd:std_logic;signal crmctgwbctb:std_logic;signal qqqjcnjzntg:std_logic;
signal bmnfdkrhvvn:std_logic;signal xpnxhwdsvfw:std_logic;signal
pqgbgwdsdms:std_logic;signal kwdkjdvmscs:std_logic;signal sqmgktwqhfz:std_logic;
signal xtkxbzvhtsv:std_logic;signal kzdbbcpdwpp:std_logic;signal
msnchvzbrqt:std_logic;signal qcbzhzptzth:std_logic;signal vjfrrdnkqtj:std_logic;
signal vswspmmdxcj:std_logic;signal cjjcvbqtckq:std_logic;signal
hrgmtcpsdzr:std_logic;signal bcvqthfzsqt:std_logic;signal hdmzrfrqzxq:std_logic;
begin xpnxhwdsvfw<=bgcgxskznzs;pqgbgwdsdms<=smvsxpgjmjj;
kwdkjdvmscs<=pbrmgfnrnxq;sqmgktwqhfz<=mrjgbfsqxpv;xtkxbzvhtsv<=bmwnqmctdkc;
kzdbbcpdwpp<=pprvvcxpxrw;msnchvzbrqt<=ptbgdzqpfjh;qcbzhzptzth<=zkngqtzrgks;
vjfrrdnkqtj<=mzbhqpgcrqx;rntfrjgxqfn<=vswspmmdxcj;jdcjstkrfpq<=cjjcvbqtckq;
nnrhkdmqgrk<=hrgmtcpsdzr;vqxxxfhknzt<=bcvqthfzsqt;tkbnpjzqwmx<=hdmzrfrqzxq;
bcvqthfzsqt<=qqqjcnjzntg;hdmzrfrqzxq<=bmnfdkrhvvn;wfqthhnhtgb:process(
xpnxhwdsvfw,kwdkjdvmscs)begin if kwdkjdvmscs='0' then qqqjcnjzntg<='0';
bmnfdkrhvvn<='0';elsif rising_edge(xpnxhwdsvfw)then qqqjcnjzntg<=kzdbbcpdwpp;
bmnfdkrhvvn<=msnchvzbrqt;end if;end process;nrczbjkrwbc:process(pqgbgwdsdms,
kwdkjdvmscs)begin if kwdkjdvmscs='0' then zmbsbbtjszd<='0';cjjcvbqtckq<='0';
crmctgwbctb<='0';hrgmtcpsdzr<='0';elsif rising_edge(pqgbgwdsdms)then
zmbsbbtjszd<=qcbzhzptzth;cjjcvbqtckq<=zmbsbbtjszd;crmctgwbctb<=vjfrrdnkqtj;
hrgmtcpsdzr<=crmctgwbctb;end if;end process;vswspmmdxcj<=xpnxhwdsvfw when(
sqmgktwqhfz or xtkxbzvhtsv)='1' else pqgbgwdsdms;end bmnqpbgpmvq;library ieee;
use ieee.std_logic_1164.all;use ieee.numeric_std.all;entity INITCFG_XF is port(
xaa:in std_logic;xab:in std_logic;xac:in std_logic;xad:in std_logic;xae:in
std_logic;xaf:in std_logic;xag:in std_logic;xah:in std_logic;xai:in std_logic;
xaj:out std_logic;xak:out std_logic;xal:out std_logic;xam:out std_logic;xan:out
std_logic);end INITCFG_XF;architecture behavior of INITCFG_XF is component
jhmkpjjmdkx port(bgcgxskznzs:in std_logic;smvsxpgjmjj:in std_logic;
pbrmgfnrnxq:in std_logic;mrjgbfsqxpv:in std_logic;bmwnqmctdkc:in std_logic;
pprvvcxpxrw:in std_logic;ptbgdzqpfjh:in std_logic;zkngqtzrgks:in std_logic;
mzbhqpgcrqx:in std_logic;rntfrjgxqfn:out std_logic;jdcjstkrfpq:out std_logic;
nnrhkdmqgrk:out std_logic;vqxxxfhknzt:out std_logic;tkbnpjzqwmx:out std_logic);
end component;begin u_jhmkpjjmdkx:jhmkpjjmdkx port map(bgcgxskznzs=>xaa,
smvsxpgjmjj=>xab,pbrmgfnrnxq=>xac,mrjgbfsqxpv=>xad,bmwnqmctdkc=>xae,
pprvvcxpxrw=>xaf,ptbgdzqpfjh=>xag,zkngqtzrgks=>xah,mzbhqpgcrqx=>xai,
rntfrjgxqfn=>xaj,jdcjstkrfpq=>xak,nnrhkdmqgrk=>xal,vqxxxfhknzt=>xam,
tkbnpjzqwmx=>xan);end behavior;