initcfg_xe.vhd

Actel Fusion System Management Development Kit UART Example. Contains Libero design using CoreABC. P

-------------------------------------------------------------------------------
-- (c) Copyright 2005 Actel Corporation
--
-- name:		initcfg_xe.vhd
-- function:	SMARTgen IP
-- Rev:			1.4 28Nov05
--
-------------------------------------------------------------------------------
library ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;entity
gpbdjfttbjd is generic(pwsjbpbwfdp:integer:=4;rszdtxvjmkk:integer:=2);port(
phtcbhxrzgc:in std_logic;cpfsfjktjsp:in std_logic;hvwtzkgfwtj:in std_logic;
ppbwmkqwrks:in std_logic_vector(rszdtxvjmkk-1 downto 0);vpvdgzxbbsp:in
std_logic_vector(rszdtxvjmkk-1 downto 0);fpppnnsbksx:out std_logic_vector(
pwsjbpbwfdp-1 downto 0));end gpbdjfttbjd;architecture zsftcmnmkdb of
gpbdjfttbjd is signal vcktjmvmkfg:std_logic;signal qqtqdjgzshf:std_logic;signal
kqgvfmthpdc:std_logic;signal rtxvrxrstjn:std_logic_vector(rszdtxvjmkk-1 downto
0);signal dcmpvpmdjpr:std_logic_vector(rszdtxvjmkk-1 downto 0);signal
tjkfbzdjjqq:std_logic_vector(pwsjbpbwfdp-1 downto 0);begin
vcktjmvmkfg<=phtcbhxrzgc;qqtqdjgzshf<=cpfsfjktjsp;kqgvfmthpdc<=hvwtzkgfwtj;
rtxvrxrstjn<=ppbwmkqwrks;dcmpvpmdjpr<=vpvdgzxbbsp;fpppnnsbksx<=tjkfbzdjjqq;
tdckqkwvkfk:process(vcktjmvmkfg,qqtqdjgzshf,kqgvfmthpdc,rtxvrxrstjn,dcmpvpmdjpr)
begin tjkfbzdjjqq<=(others=>'0');if(not vcktjmvmkfg and kqgvfmthpdc)='1' then
tjkfbzdjjqq(to_integer(unsigned(dcmpvpmdjpr)))<='1';elsif(not vcktjmvmkfg and
qqtqdjgzshf)='1' then tjkfbzdjjqq(to_integer(unsigned(rtxvrxrstjn)))<='1';else
tjkfbzdjjqq<=(others=>'0');end if;end process tdckqkwvkfk;end zsftcmnmkdb;
library ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;entity
INITCFG_XE is generic(MAX_CLIENT:integer:=4;MAX_CLIENT_BITS:integer:=2);port(
xaa:in std_logic;xab:in std_logic;xac:in std_logic;xad:in std_logic_vector(
MAX_CLIENT_BITS-1 downto 0);xae:in std_logic_vector(MAX_CLIENT_BITS-1 downto 0);
xaf:out std_logic_vector(MAX_CLIENT-1 downto 0));end INITCFG_XE;architecture
behavior of INITCFG_XE is component gpbdjfttbjd generic(pwsjbpbwfdp:integer:=4;
rszdtxvjmkk:integer:=2);port(phtcbhxrzgc:in std_logic;cpfsfjktjsp:in std_logic;
hvwtzkgfwtj:in std_logic;ppbwmkqwrks:in std_logic_vector(rszdtxvjmkk-1 downto 0)
;vpvdgzxbbsp:in std_logic_vector(rszdtxvjmkk-1 downto 0);fpppnnsbksx:out
std_logic_vector(pwsjbpbwfdp-1 downto 0));end component;begin
u_gpbdjfttbjd:gpbdjfttbjd generic map(pwsjbpbwfdp=>MAX_CLIENT,
rszdtxvjmkk=>MAX_CLIENT_BITS)port map(phtcbhxrzgc=>xaa,cpfsfjktjsp=>xab,
hvwtzkgfwtj=>xac,ppbwmkqwrks=>xad,vpvdgzxbbsp=>xae,fpppnnsbksx=>xaf);end
behavior;