initcfg_xd.vhd

Actel Fusion System Management Development Kit UART Example. Contains Libero design using CoreABC. P

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-- (c) Copyright 2005 Actel Corporation
--
-- name:		initcfg_xd.vhd
-- function:	SMARTgen IP
-- Rev:			1.4 28Nov05
--
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library ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;entity
dxwqxgdccxc is generic(pjbfkczqqqn:integer:=10);port(xssfvmhwvqr:in std_logic;
vzkrtwmkbfp:in std_logic;wpfsqtfqtmx:in std_logic;xkvhpkkjhmx:in std_logic;
fjnpbpzwdfq:in std_logic_vector(17 downto 0);frghwwdcnrp:in std_logic_vector(
pjbfkczqqqn-1 downto 0);wqwwrvhjsjn:in std_logic_vector(1 downto 0);
fpqczqbtsss:in std_logic;rjbphxwnnvg:in std_logic;nxgsfjcdzzs:out
std_logic_vector(17 downto 0);vndvfnkzrjh:out std_logic_vector(pjbfkczqqqn-1
downto 0);qgjhdcsjsnm:out std_logic;tgdcsdwhfxk:out std_logic);end dxwqxgdccxc;
architecture cmvhvtvbzkh of dxwqxgdccxc is signal gnmdxrqrdgs:unsigned(
pjbfkczqqqn-1 downto 0);signal kftxkfpnstb:std_logic;signal
whjmwvkhppg:std_logic;signal mzjkcvxthjd:unsigned(17 downto 0);signal
ggfvvjbkdws:unsigned(17 downto 0);signal zwwkvpdkxxz:unsigned(17 downto 0);
signal mbvdnqcvcsk:unsigned(17 downto 0);signal mzjgqbcjvkt:unsigned(17 downto
0);signal dkjzqmrkvwb:unsigned(17 downto 0);signal fkkgzgqqjcg:unsigned(17
downto 0);signal svsgrbsrwbx:std_logic;signal ddqqkfbmpxc:std_logic;signal
kzgsdsznrwv:std_logic;signal tnjvgqqhdkd:std_logic;signal
tsxbrzwpbfb:std_logic_vector(17 downto 0);signal nmkgbzzhvms:std_logic_vector(
pjbfkczqqqn-1 downto 0);signal brqjfzhdpxc:std_logic_vector(1 downto 0);signal
cjprksxkhsp:std_logic;signal cpvgpntqkzz:std_logic;signal
tqxgjghczwp:std_logic_vector(17 downto 0);signal xpfhwvtdxqs:std_logic_vector(
pjbfkczqqqn-1 downto 0);signal hvsmtdhhdwv:std_logic;signal
xzczkwrmrng:std_logic;begin svsgrbsrwbx<=xssfvmhwvqr;ddqqkfbmpxc<=vzkrtwmkbfp;
kzgsdsznrwv<=wpfsqtfqtmx;tnjvgqqhdkd<=xkvhpkkjhmx;tsxbrzwpbfb<=fjnpbpzwdfq;
nmkgbzzhvms<=frghwwdcnrp;brqjfzhdpxc<=wqwwrvhjsjn;cjprksxkhsp<=fpqczqbtsss;
cpvgpntqkzz<=rjbphxwnnvg;nxgsfjcdzzs<=tqxgjghczwp;vndvfnkzrjh<=xpfhwvtdxqs;
qgjhdcsjsnm<=hvsmtdhhdwv;tgdcsdwhfxk<=xzczkwrmrng;hvsmtdhhdwv<=kftxkfpnstb;
xzczkwrmrng<=whjmwvkhppg;xpfhwvtdxqs<=std_logic_vector(gnmdxrqrdgs);
tqxgjghczwp<=std_logic_vector(fkkgzgqqjcg);grtwdzjfrbn:if pjbfkczqqqn<18
generate gdjbdpknqtc:for i in pjbfkczqqqn to 17 generate mzjkcvxthjd(i)<='0';
end generate;mzjkcvxthjd(pjbfkczqqqn-1 downto 0)<=gnmdxrqrdgs(pjbfkczqqqn-1
downto 0);end generate;xxpqsnkjmrr:if pjbfkczqqqn>=18 generate mzjkcvxthjd(17
downto 0)<=gnmdxrqrdgs(17 downto 0);end generate;ggfvvjbkdws<=(mzjkcvxthjd(16
downto 0)&'0')when brqjfzhdpxc /="00" else mzjkcvxthjd;zwwkvpdkxxz<="00000"&(
unsigned(tsxbrzwpbfb(17 downto 12)&tsxbrzwpbfb(6 downto 0)));
mbvdnqcvcsk<=zwwkvpdkxxz when cpvgpntqkzz='1' else unsigned(tsxbrzwpbfb);
dkjzqmrkvwb<=unsigned(mbvdnqcvcsk)+ ggfvvjbkdws;mzjgqbcjvkt<=dkjzqmrkvwb(12
downto 7)&"00000"&dkjzqmrkvwb(6 downto 0);fkkgzgqqjcg<=mzjgqbcjvkt when
cpvgpntqkzz='1' else dkjzqmrkvwb;jvbvzqvvxpc:process(svsgrbsrwbx,ddqqkfbmpxc)
begin if ddqqkfbmpxc='0' then gnmdxrqrdgs<=(others=>'0');kftxkfpnstb<='0';elsif
rising_edge(svsgrbsrwbx)then if tnjvgqqhdkd='1' then gnmdxrqrdgs<=(others=>'0');
elsif kzgsdsznrwv='1' then gnmdxrqrdgs<=gnmdxrqrdgs + 1;end if;if(
gnmdxrqrdgs=unsigned(nmkgbzzhvms))then kftxkfpnstb<='1';elsif tnjvgqqhdkd='1'
then kftxkfpnstb<='0';end if;end if;end process jvbvzqvvxpc;gncnhthqqtj:process(
fkkgzgqqjcg,brqjfzhdpxc,cjprksxkhsp)begin if fkkgzgqqjcg(6 downto 1)="111111"
and(fkkgzgqqjcg(0)or brqjfzhdpxc(0)or brqjfzhdpxc(1))='1' then
whjmwvkhppg<=cjprksxkhsp;else whjmwvkhppg<='0';end if;end process gncnhthqqtj;
end cmvhvtvbzkh;library ieee;use ieee.std_logic_1164.all;use
ieee.numeric_std.all;entity INITCFG_XD is generic(MAX_WORD_BIT:integer:=10);
port(xaa:in std_logic;xab:in std_logic;xac:in std_logic;xad:in std_logic;xae:in
std_logic_vector(17 downto 0);xaf:in std_logic_vector(MAX_WORD_BIT-1 downto 0);
xag:in std_logic_vector(1 downto 0);xah:in std_logic;xai:in std_logic;xaj:out
std_logic_vector(17 downto 0);xak:out std_logic_vector(MAX_WORD_BIT-1 downto 0);
xal:out std_logic;xam:out std_logic);end INITCFG_XD;architecture behavior of
INITCFG_XD is component dxwqxgdccxc generic(pjbfkczqqqn:integer:=10);port(
xssfvmhwvqr:in std_logic;vzkrtwmkbfp:in std_logic;wpfsqtfqtmx:in std_logic;
xkvhpkkjhmx:in std_logic;fjnpbpzwdfq:in std_logic_vector(17 downto 0);
frghwwdcnrp:in std_logic_vector(pjbfkczqqqn-1 downto 0);wqwwrvhjsjn:in
std_logic_vector(1 downto 0);fpqczqbtsss:in std_logic;rjbphxwnnvg:in std_logic;
nxgsfjcdzzs:out std_logic_vector(17 downto 0);vndvfnkzrjh:out std_logic_vector(
pjbfkczqqqn-1 downto 0);qgjhdcsjsnm:out std_logic;tgdcsdwhfxk:out std_logic);
end component;begin u_dxwqxgdccxc:dxwqxgdccxc generic map(
pjbfkczqqqn=>MAX_WORD_BIT)port map(xssfvmhwvqr=>xaa,vzkrtwmkbfp=>xab,
wpfsqtfqtmx=>xac,xkvhpkkjhmx=>xad,fjnpbpzwdfq=>xae,frghwwdcnrp=>xaf,
wqwwrvhjsjn=>xag,fpqczqbtsss=>xah,rjbphxwnnvg=>xai,nxgsfjcdzzs=>xaj,
vndvfnkzrjh=>xak,qgjhdcsjsnm=>xal,tgdcsdwhfxk=>xam);end behavior;