udc_ahb.h.orig

Spearhead2000的bootloader

/******************************************************************************
**                                                                           **
**  Copyright (c) 2002 ST Microelectronics                                   **
**  All rights reserved                                                      **
**                                                                           **
**      Author    :  Armando Visconti                                        **
**      Revision  :  1.0                                                     **
**                                                                           **
**                                                                           **
**                                                                           **
*******************************************************************************/
#ifndef __SPEAr_USB_H
#define __SPEAr_USB_H

#ifdef     __cplusplus
extern  "C" {           /* C declarations in C++     */
#endif


#define VUINTP                          (volatile unsigned int *) 
#define TASK_HAS_THE_RIGHTS(taskp)      ( (CurrentTaskOwner == NULL) || (CurrentTaskOwner == NU_Current_Task_Pointer()))

/*****************************************************************************
 * Defines for USB
 *****************************************************************************/
/*
 * USB Base Address 
 */

#define USB_Base     0x10000000         // I/O Base Address of USB

 
/* DMA_USB Descriptor definition*/

typedef struct
        {
           int    DmaUsb_Status;
           int    DmaUsb_Reserved;
           int    DmaUsb_Data1;
           int    DmaUsb_Data2;
        } DmaUsbSetupDescr;
        
typedef struct DmaUsbBulkDescr
        {
           int                      DmaUsb_Status;
           int                      DmaUsb_Reserved;
           char                     *DmaUsb_Addr;
           struct DmaUsbBulkDescr   *DmaUsb_Next;
        } DmaUsbBulkDescr;  
        
#define  DmaUsb_HostRdy            0x00000000
#define  DmaUsb_DmaBsy             0x40000000
#define  DmaUsb_DmaDone            0x80000000
#define  DmaUsb_HostBsy            0xC0000000
#define  DmaUsb_BS_Mask            0xC0000000
#define  DmaUsb_Success            0x00000000
#define  DmaUsb_DescrErr           0x10000000
#define  DmaUsb_BufErr             0x30000000
#define  DmaUsb_RXSts_Mask         0x30000000
#define  DmaUsb_LastDescr          0x08000000
#define  DmaUsb_Len_Mask           0x0000FFFF



/*****************************************************************************
* In and Out EndPoint's Bases
*****************************************************************************/

#define  In_Endp0                  0x00000000
#define  In_Endp1                  0x00000020
#define  In_Endp2                  0x00000040
// #define  In_Endp4                  0x00000080

#define  Out_Endp0                 0x00000200
#define  Out_Endp1                 0x00000220
#define  Out_Endp2                 0x00000240
// #define  Out_Endp3                 0x00000260

/*****************************************************************************
 * Endpoint specific CSRs
 *****************************************************************************/

/*
 * Endpoint Control Register
 */

#define  Endp_Cntl                 (USB_Base + 0x000)
#define  Endp_Cntl_Msk_In          0x0000003b
#define  Endp_Cntl_Msk_Out         0x00000035
#define  Endp_Cntl_Rst             0x00000000
#define  Endp_Cntl_Msk_r           0xffffffff

                           /* Values ....*/

#define  Endp_Cntl_STALL           0x00000001      /* RW */
#define  Endp_Cntl_FLUSH           0x00000002      /* RW */        
#define  Endp_Cntl_SNOOP           0x00000004      /* RW */
#define  Endp_Cntl_POLL            0x00000008      /* RW */
#define  Endp_Cntl_Control         0x00000000      /* RW */
#define  Endp_Cntl_Iso             0x00000010      /* RW */
#define  Endp_Cntl_Bulk            0x00000020      /* RW */
#define  Endp_Cntl_Int             0x00000030      /* RW */
#define  Endp_Cntl_NAK             0x00000040      /* RW */
#define  Endp_Cntl_SNAK 	   0x00000080	   /* RW */
#define  Endp_Cntl_CNAK 	   0x00000100	   /* RW */
#define  Endp_Cntl_RRDY 	   0x00000200	   /* RW */

/*
 * Endpoint Satus Register
 */
                           
#define  Endp_Status               (USB_Base + 0x004)
#define  Endp_Status_Msk           0x003fffff
#define  Endp_Status_Rst           0x00000000
#define  Endp_Status_Msk_r         0xff8007cf
   
                           /* Values ....*/
                           
#define  Endp_Status_PIDMsk        0x0000000f      /* RO */
#define  Endp_Status_OUTMsk        0x00000030      /* RO */
#define  Endp_Status_OUT_none      0x00000000
#define  Endp_Status_OUT_Data      0x00000010
#define  Endp_Status_OUT_Setup     0x00000020
#define  Endp_Status_IN            0x00000040      /* RW */
#define  Endp_Status_BUFFNAV       0x00000080      /* RW */   
#define  Endp_Status_FATERR        0x00000100      /* RW */
#define  Endp_Status_HOSTBUSERR    0x00000200      /* RW */  
#define  Endp_Status_TDC           0x00000400      /* RW */
#define  Endp_Status_RXPKTMsk      0x003ff800      /* RO */

/*
 * Endpoint Buffer Size Register for IN ; Receive Packet Frame Number for OUT
 */                           
                           
#define  Endp_BSorFN            (USB_Base + 0x008)
#define  Endp_BSorFN_Msk_In     0x0000ffff
#define  Endp_BSorFN_Msk_Out    0x00000000
#define  Endp_BSorFN_Rst        0x00000000
#define  Endp_BSorFN_Msk_r      0xffff0000

                           /* Values ....*/

#define  Endp_BSorFN_BUFFSIZE   0x0000ffff        /* RW (FOR IN ENDPOINT)*/                 
#define  Endp_BSorFN_FRAMENUM   0x0000ffff        /* RO (FOR OUT ENDPOINT)*/             
#define  Endp_BSorFN_FRAMENUM_Base   0x00010000        /* RO (FOR OUT ENDPOINT)*/             

/*
 * Enpoint maximum Packet Size Register
 */                           

#define  Endp_Max_Pack_Size        (USB_Base + 0x00C)    /* RW */
#define  Endp_Max_Pack_Size_Msk    0x0000ffff
#define  Endp_Max_Pack_Size_Rst    0x00000000
#define  Endp_Max_Pack_Size_Msk_r  0xffffffff
#define  Endp_BufSize_OUT_Msk	   0xffff0000
#define  Endp_BufSize_OUT_Base     0x00010000

#define  CONTROL_ENDPT_MAX_SIZE_HS      64
#define  BULK_ENDPT_DMA_MAX_SIZE_HS     512
#define  BULK_ENDPT_SLAVE_MAX_SIZE_HS   512
#define  CONTROL_ENDPT_MAX_SIZE_FS      64
#define  BULK_ENDPT_DMA_MAX_SIZE_FS     64
#define  BULK_ENDPT_SLAVE_MAX_SIZE_FS   64

                                                     
/*
 * Setup Buffer Pointer for CONTROL OUT (ENDPOINT 0)
 */                           
                           
#define  Out_Endp_Setup_buf_point      (USB_Base + 0x010)
#define  Out_Endp_Setup_buf_point_Msk  0xffffffff                             
#define  Out_Endp_Setup_buf_point_Rst  0x00000000
#define  Out_Endp_Setup_buf_point_Msk_r  0xffffffff                             

                           
/*
 * Descriptor Pointer 
 */                            
                                                     
#define  Endp_Desc_point           (USB_Base + 0x014)
#define  Endp_Desc_point_Msk        0xffffffff
#define  Endp_Desc_point_Rst        0x00000000
#define  Endp_Desc_point_Msk_r      0xffffffff


/*****************************************************************************
* UDC_AHB Registers
*****************************************************************************/  

/*
 * Device Configuration Register
 */

#define Dev_Conf                    (USB_Base + 0x400)
#define Dev_Conf_Msk                0x0000003f
#define Dev_Conf_Rst                0x00000000

                           /* Values ....*/
                           
#define Dev_Conf_HS_SPEED           0x00000000     /* RW */
#define Dev_Conf_LS_SPEED           0x00000002     /* RW */
#define Dev_Conf_FS_SPEED           0x00000003     /* RW */
#define Dev_Conf_REMWAKEUP          0x00000004     /* RW */
#define Dev_Conf_SELFPOW            0x00000008     /* RW */
#define Dev_Conf_SYNCFRAME          0x00000010     /* RW */
#define Dev_Conf_PHYINT_8           0x00000020     /* RW */                           
#define Dev_Conf_PHYINT_16          0x00000000     /* RW */
#define Dev_Conf_UTMI_BIDIR	    0x00000040     /* RW */
#define Dev_Conf_STATUS_STALL	    0x00000080     /* RW */
/*
 * Device Control Register
 */                          

#define Dev_Cntl                    (USB_Base + 0x404)
#define Dev_Cntl_Msk                0xffffffff
#define Dev_Cntl_Rst                0x00000000

                           /* Values ....*/

#define Dev_Cntl_RESUME             0x00000001     /* RW */
#define Dev_Cntl_TFFLUSH            0x00000002     /* RW */                         
#define Dev_Cntl_RxDMAEn            0x00000004     /* RW */                         
#define Dev_Cntl_TxDMAEn            0x00000008     /* RW */                         
#define Dev_Cntl_DescrUpd           0x00000010     /* RW */                         
#define Dev_Cntl_BigEnd             0x00000020     /* RW */                         
#define Dev_Cntl_BufFill            0x00000040     /* RW */                         
#define Dev_Cntl_TshldEn            0x00000080     /* RW */                         
#define Dev_Cntl_BurstEn            0x00000100     /* RW */                         
#define Dev_Cntl_DMAMode            0x00000200     /* RW */                         
#define Dev_Cntl_SoftDisconnect     0x00000400     /* RW */
#define Dev_Cntl_ScaleDown	    0x00000800     /* RW */
#define Dev_Cntl_BurstLenU          0x00010000     /* RW */                         
#define Dev_Cntl_BurstLenMsk        0x00ff0000     /* RW */                         
#define Dev_Cntl_TshldLenU          0x01000000     /* RW */                         
#define Dev_Cntl_TshldLenMsk        0xff000000     /* RW */                         
                           
/*
 * Device Status register
 */                            

#define Dev_Stat                    (USB_Base + 0x408)
#define Dev_Stat_Msk                0x00000000
#define Dev_Stat_Rst                0x00000000

                           /* Values ....*/
                           
#define Dev_Stat_CFG                0x0000000f     /* RO */
#define Dev_Stat_INTF               0x000000f0     /* RO */
#define Dev_Stat_ALT                0x00000f00     /* RO */
#define Dev_Stat_SUSP               0x00001000     /* RO */
#define Dev_Stat_ENUM               0x00006000     /* RO */
#define Dev_Stat_ENUM_SPEED_HS      0x00000000     /* RO */  
#define Dev_Stat_ENUM_SPEED_FS      0x00002000     /* RO */
#define Dev_Stat_ENUM_SPEED_LS      0x00004000     /* RO */
#define Dev_Stat_RXFIFO_EMPTY	    0x00008000     /* RO */
#define Dev_Stat_PHY_Err	    0x00010000     /* RO */
#define Dev_Stat_TS                 0xf0000000     /* RO */                           
                           
/*
 * Device Interrupt Register
 */                           
                           
#define Dev_Int                     (USB_Base + 0x40C)
#define Dev_Int_Msk                 0x0000007f                          
#define Dev_Int_Rst                 0x00000000

                           /* Values ....*/
                           
#define Dev_Int_SETCFG              0x00000001     /* RW */ 
#define Dev_Int_SETINTF             0x00000002     /* RW */
#define Dev_Int_INACTIVE            0x00000004     /* RW */
#define Dev_Int_USBRESET            0x00000008     /* RW */
#define Dev_Int_SUSPUSB             0x00000010     /* RW */
#define Dev_Int_SOF                 0x00000020     /* RW */
#define Dev_Int_ENUM                0x00000040     /* RW */