init (1).s

Spearhead2000的bootloader

/*;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
//; 
//; ACCENT Srl
//; 
//; PNCU - SIM_2 TEST
//;
//; Version and Release Control Information:
//;
//; File 		: 	init.s
//; File Rev.	: 	1.0
//; Authors	: 	A. Visconti - ST Microelectronics S.p.A.
//;
//;		
//;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
//;
//; ************************************************
//; *  This routine contains the exeptions vector and
//; *  the code to initialize the system at reset time.
//; ************************************************
//;
//;


//;-----------------------------------------------------------------------------------
  //  INCLUDE mmu946T.s
    //INCLUDE arm.equ
    
//;-----------------------------------------------------------------------------------
    
//   AREA   INIT, CODE, READONLY

//;-----------------------------------------------------------------------------------
*/
   
#define SDRAM_Limit  0x04000000
                                                                                                                             
                                                                                                                             
#define SVCStack   SDRAM_Limit
#define FIQStack   SVCStack - SVCStackSize
#define IRQStack   FIQStack - FIQStackSize
#define ABTStack   IRQStack - IRQStackSize
#define UNDStack   ABTStack - ABTStackSize
#define USRStack   UNDStack - UNDStackSize
#define PrgLimit   USRStack - USRStackSize
                                                                                                                             
#define SVCStackSize  512
#define FIQStackSize   512
#define IRQStackSize  2048
#define ABTStackSize  0
#define UNDStackSize  0
#define USRStackSize  4096

#define MODE_BITS     0x1F
#define DISABLE_FIQ   0x40
#define DISABLE_IRQ   0x80
#define MODE_USR_32   0x10
#define MODE_FIQ_32   0x11
#define MODE_IRQ_32   0x12
#define MODE_ABT_32   0x17
#define MODE_UND_32   0x1B
#define INTERRUPT_BITS 0xC0

.global MY_ENTRY
MY_ENTRY:
   
   B reset             /* ; @0x00000 : Reset*/
  
    
   B undefined_handler	/*; @0x00004 : undefined instr.*/
   
   B soft_handler       /*; @0x00008 : software int.*/
   
   B pabort_handler	/*; @0x0000C : prefetch abort*/
   
   B dabort_handler	/*; @0x00010 : data abort*/
   
   B reserved_handler	/*; @0x00014 : reserved */
   
/*      IMPORT IRQGeneralHandler*/
   B IRQGeneralHandler  /*; @0x00018 : irq*/
         

/*   IMPORT FIQGeneralHandler*/
   B FIQGeneralHandler  /*; @0x0001C : fiq*/

undefined_handler:
soft_handler:
pabort_handler:
dabort_handler:
reserved_handler:

here:
 	B here  /* ;Loop forever if an invalid vector is reached.*/

/*reset   ROUT*/
reset:

/*;############################################### REMAP #######################################################
//;    LDR     a3, =0x16000038 ; writes '1' in AHB remap register to do remap
   
//;    LDR     a1, =0x1200306c   
//;    MOV     a2, #0x01
//;    STR     a2, [a1, #0]
    
//;    mov     pc, a3  ; after remap the flash is mapped to 0x16000000 so the code jump to this address
//;#############################################################################################################
	
//    ; * Initialise ARM MPMC PL175 *
//    ; PL175_init() ;
//    ;
//;    IMPORT  PL175_init_SDR
//;    BL PL175_init_SDR
   
//;	 LDR     a3, =0x00000044
//;	 mov     pc, a3
*/
    
	 BL APB_SETUP

  /*  ;BL COPY_CODE*/

/*    ; Initialize the Stack Pointer registers*/
/*    ; When returning the ARM is in user mode*/
    BL stack_init

/*    ; Copy variables in RAM (RW + ZI)*/
    BL	CopyDataInDram

/*   IMPORT C_Entry			; The C main routine has C_main label. 	*/
/*   C_Entry: */
   LDR R14, =C_Entry	/*; Get the address of the C entry point.*/
   MOV pc, R14


/*; ************************************************
//; * init MPU and enable cache 
//; ************************************************
*/

/*uHALMPU_SETUP ROUT*/
uHALMPU_SETUP:

   MOV r4,    #0x0000003F	    /*; Reg0 - Base(00000000), Size(11111=4G)*/
   MCR p15,0x0,r4,c6,c0,0							      
   MCR p15,0x0,r4,c6,c0,1							      

   MOV r4,    #0x00000031	    /*; Reg1 - Base(00000000), Size(11000=32MB)*/
   MCR p15,0x0,r4,c6,c1,0							      

   LDR r4,    =0x10000035	    /*; Reg2 - Base(10000000), Size(11010=128MB)*/
   MCR p15,0x0,r4,c6,c2,0							      

   LDR r4,    =0x18000035	    /*; Reg3 - Base(18000000), Size(11010=128MB)	*/ 
   MCR p15,0x0,r4,c6,c3,0							      

/*   ; reg c5 setting*/						       
   MOV r4,    #0x00FF		    /*; Reg 0 - 3 : AP == 11*/
   MCR p15,0x0,r4,c5,c0,0							       
   MCR p15,0x0,r4,c5,c0,1							       

/*   ; reg c2 setting	*/
/*   ;MOV r4,    #0xE		    ; Reg 1/2/3 -- D Cache bit set*/
   MOV r4,    #0x6		   /* ; Reg 1/2 -- D Cache bit set*/	       
   MCR p15,0x0,r4,c2,c0,0							       

   MOV r4,    #0x2		   /* ; Reg 1 -- I Cache bit set */
   MCR p15,0x0,r4,c2,c0,1							       

   MRC p15, 0, r0, c1, c0, 0							       
   LDR r1,  =0x1005		   /* ; MPU_ON - ICACHE ON - DCACHE_ON*/
   ORR r0,     r0, r1									 
   MCR p15, 0, r0, c1, c0, 0								 

   MOV pc, R14


/*; ************************************************
//; *  Routine to initialize the stack.
//; ************************************************

//;-------------------------------------------------------------------------------
//; 	BASE ADDRESSES
//;-------------------------------------------------------------------------------

//;;USRStack0	EQU	0x01800
//;;IRQStack0	EQU	0x01840
//;;FIQStack0	EQU	0x01880
//;;SVCStack0	EQU	0x018C0
*/


/*SDRAM_Limit         EQU    0x04000000  


//SVCStack      EQU     SDRAM_Limit
//FIQStack      EQU     SVCStack - SVCStackSize
//IRQStack      EQU     FIQStack - FIQStackSize
//ABTStack      EQU     IRQStack - IRQStackSize
//UNDStack      EQU     ABTStack - ABTStackSize
//USRStack      EQU     UNDStack - UNDStackSize
//PrgLimit      EQU     USRStack - USRStackSize

//SVCStackSize  EQU     512
//FIQStackSize  EQU     512
//IRQStackSize  EQU     2048
//ABTStackSize  EQU     0
//UNDStackSize  EQU     0
//USRStackSize  EQU     4096

//; ************************************************
//; * init ITCM 
//; ************************************************
*/

/*ITCM_SETUP ROUT*/
ITCM_SETUP:


/*;   IMPORT  |Image$$FLASH$$Length|
//;   LDR R1 , =|Image$$FLASH$$Length|      
//;	ADD R1, R1 ,#10                
   
	
//;	MOV R2, #1       ;TCM enable bit

//;   ; Set-Up Region Register
//;   ; Preserve Misterius SBZ Bit...
//;   RD_ITCM_REGION_REGISTER r4
//;   ORR     r4,r4,r2
//;   WR_ITCM_REGION_REGISTER r4

//;   MOV R12, #0x16000000 
//;	MOV R13, #0x00000000 
	 

//; ;  SET_ITCM_LOAD_MODE R2
//; ;  ENABLE_ITCM R2
//;CopyLoop
//;   LDMIA R12, {R2 - R11}    ; Load 10 registers from flash
//;   STMIA R13!, {R2 - R11}   ; Store 8 regs into ITCM (NB:load mode is enable!)
//;   CMP R1, R13
//;   BGT CopyLoop
*/

   MOV pc, R14
/*; ************************************************
//; ***********************************************
//;  APB Interface Setup
//; ***********************************************
*/
/*APB_SETUP ROUT*/
APB_SETUP:
   MOV R2 , #0xffffffff   /*; number of periph*/
	MOV R12, #0x12000000  
   

   STR R2, [R12, #0x20]  /*; disable write protection*/
   STR R2, [R12, #0x40] /*; disable read  protection*/


   MOV pc, R14



/*; ************************************************
//; * COPY CODE
//; ************************************************
*/
/*COPY_CODE ROUT*/
COPY_CODE:

/*;   IMPORT  |Load$$FLASH$$Base|
//;   IMPORT  |Image$$DDR_SDRAM$$Base|        ; Base of RAM to initialise
//;   IMPORT  |Image$$DDR_SDRAM$$Length|      ; Len of RAM data
//;   IMPORT  |Image$$FLASH$$Length|
//;   IMPORT  |Image$$RO$$Base|
//;   IMPORT  |Load$$DDR_SDRAM$$Base| 
//; ;Copy code in DRAM
//;   LDR     r0, =|Load$$FLASH$$Base|     ; Get pointer to ROM data
//;   LDR     r1, =|Image$$RO$$Base|    ; and RAM copy
//;   LDR     r3, =|Image$$FLASH$$Length|  ; Zero init base => top of initialised data
//;   MOV     r4, #0
//;   CMP     r0, r1                  ; Check that they are different
//;   BEQ    end1
//;loop1   CMP     r4, r3                  ; Copy init data
//;   LDRLT   r2, [r0], #4
//;   STRLT   r2, [r1], #4
//;   ADDLT   r4, r4, #4
//;   BLT     loop1
//;end1 
*/
 MOV pc, R14 

/*;copy data in dram*/
/*CopyDataInDram ROUT  */
CopyDataInDram:


/*; 
//;   LDR     r0, =|Load$$DDR_SDRAM$$Base|     ; Get pointer to ROM data
//;   LDR     r1, =|Image$$DDR_SDRAM$$Base|    ; and RAM copy
//;   LDR     r3, =|Image$$DDR_SDRAM$$Length|  ; Zero init base => top of initialised data
//;   MOV     r4, #0
//;   CMP     r0, r1                  ; Check that they are different
//;   BEQ    end2
//;loop2   CMP     r4, r3                  ; Copy init data
//;   LDRLT   r2, [r0], #4
//;   STRLT   r2, [r1], #4
//;   ADDLT   r4, r4, #4
//;   BLT     loop2
//;end2 
*/
 MOV pc, R14

/*stack_init ROUT*/
stack_init:

/*; Setup Supervisor Stack*/
   LDR     R13, =SVCStack
   MOV     R3,  R14            /*   ; Copy Return address*/

/*;Enter FIQ Mode and set up its stack*/
   MRS     R0, CPSR                        /*;get CPSR*/
   BIC     R0, R0, #MODE_BITS              /*; clear mode bit*/
   ORR     R1, R0, #(DISABLE_IRQ + DISABLE_FIQ + MODE_FIQ_32)
   MSR     CPSR_c, R1                      /*;Enter FIQ Mode*/
   LDR     SP, =FIQStack                   /*;Setup FIQ stack pointer*/

/*;Enter IRQ Mode and set up its stack*/
   MRS     R0, CPSR                        /*;get CPSR*/
   BIC     R0, R0, #MODE_BITS              /*; clear mode bit*/
   ORR     R1, R0, #(DISABLE_IRQ + DISABLE_FIQ + MODE_IRQ_32)
   MSR     CPSR_c, R1                      /*;Enter IRQ Mode*/
   LDR     SP, =IRQStack                   /*;Setup IRQ stack pointer*/

/*;Enter ABT Mode and set up its stack*/
   BIC     R0, R0, #MODE_BITS
   ORR     R1, R0, #(DISABLE_IRQ + DISABLE_FIQ + MODE_ABT_32)
   MSR     CPSR_c, R1                      /*;Enter ABT Mode*/
   LDR     SP, =ABTStack                   /*;Setup ABT stack pointer*/

/*;Enter Undefined Mode and set up its stack*/
   BIC     R0, R0, #MODE_BITS
   ORR     R1, R0, #(DISABLE_IRQ + DISABLE_FIQ + MODE_UND_32)
   MSR     CPSR_c, R1                     /* ;Enter UND Mode*/
/*   ;MOV     R2, #MODE_USR_32*/
/*   ;MSR     SPSR_c, R2                      ;Set SPSR to User Mode*/
   LDR     SP, =UNDStack                  /* ;Setup ABT stack pointer*/

/*;Enter USER mode setting the IRQ interrupt*/

   BIC     R0, R0, #MODE_BITS
   BIC     R0, R0, #INTERRUPT_BITS         /*;enable FIQ/ IRQ*/
   ORR     R1, R0, #(MODE_USR_32)
   MSR     CPSR_c, R1                      /*;Enter USR Mode and set IRQ*/
   LDR     SP, =USRStack                   /*;Setup USR stack pointer*/

/*; Return to the main asm routine*/
/*; Note that User & SuperVisor link register aren't the same.*/
   MOV     PC, R3


/*   END*/
 .end