📄 udc_ahb.h
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#define Endp_Int (USB_Base + 0x414)#define Endp_Int_Msk 0x00000000#define Endp_Int_Rst 0x00000000 /* Values ....*/ #define Endp_Int_INEP 0x0000ffff /* RC */#define Endp_Int_OUTEP 0xffff0000 /* RC */#define Endp0_Int_CtrlIN 0x00000001#define Endp1_Int_BulkIN 0x00000002#define Endp2_Int_BulkIN 0x00000004#define Endp0_Int_CtrlOUT 0x00010000#define Endp1_Int_BulkOUT 0x00020000#define Endp2_Int_BulkOUT 0x00040000 /* Values ....*/ /*#define Endp_Int_INEP 0x0000ffff RW #define Endp_Int_OUTEP 0xffff0000 RW #define Endp_Int_OUTEP_Base 0x00010000 RW */ /* * Endpoint Interrupt Mask Register */ #define Endp_Int_Mask (USB_Base + 0x418)#define Endp_Int_Mask_Msk 0xffffffff#define Endp_Int_Mask_Rst 0x00000000 /* Values ....*/ #define Endp_Int_INEPMsk 0x0000ffff /* RW */#define Endp_Int_OUTEPMsk 0xffff0000 /* RW */#define Endp0_Int_CtrlINMsk 0x00000001#define Endp1_Int_BulkINMsk 0x00000002#define Endp2_Int_BulkINMsk 0x00000004#define Endp0_Int_CtrlOUTMsk 0x00010000#define Endp1_Int_BulkOUTMsk 0x00020000#define Endp2_Int_BulkOUTMsk 0x00040000 /***************************************************************************** * UDC Registers: If the core is programmed not to decode the Get Descriptor Command (as in this case) all the parts commented are not used; else if the core is programmed to decode the Get Descriptor Command you must uncomment the parts here below and comment " #define DevdescSetupcomm_addr_Msk 0x0000ffff" see "Device Controller (UDC20) Core Ver.1.0b" *****************************************************************************/ /* * Device Descriptor/Setup Command Address register : * This register (address) is used for all endpoint and when the core drives the setup commands * not decoded by the core */ #define DevdescSetupcomm_addr (USB_Base + 0x500)#define DevdescSetupcomm_addr_Msk 0x0000ffff#define DevdescSetupcomm_addr_Rst 0x00000000 /* Values ....*/ #define DevdescSetupcomm_addr_SCAP 0x0000ffff /* RW */ #define DevdescSetupcomm_addr_DDAP 0xffff0000 /* RW */ /* * Other Speed Configuration/Qualifier Descriptor address register */ /*#define Oth_speed_conf_Qual_desc_addr (USB_Base + 0x504))#define Oth_speed_conf_Qual_desc_addr_Msk 0xffffffff#define Oth_speed_conf_Qual_desc_addr_Rst 0x00000000*/ /* Values ....*/ /*#define Oth_speed_conf_desc_addr 0x0000ffff RW #define Qual_desc_addr_pointer 0xffff0000 RW */ /* * Endpoint NE information register: RW * A register is dedicated to each implemented andpoint */ /************************** Default **************************************************** * * * #define Endp_NE (USB_Base + 0x504)) * * #define Endp_NE_Msk 0x3fffffff * * #define Endp_NE_Rst 0x00000000 * * * * Values .... * * * * #define Endp_NE_EPNUM 0x0000000f * * #define Endp_NE_EPDIR_OUT 0x00000000 * * #define Endp_NE_EPDIR_IN 0x00000010 * * #define Endp_NE_EPTYPE_CNTR 0x00000000 * * * #define Endp_NE_EPTYPE_ISO 0x00000020 * * #define Endp_NE_EPTYPE_BULK 0x00000040 * * #define Endp_NE_EPTYPE_INT 0x00000060 * * #define Endp_NE_CFG_NUM 0x00000780 * * #define Endp_NE_INTF_NUM 0x00007800 * * #define Endp_NE_ALT_SETT 0x00078000 * * #define Endp_NE_MAX_PKT_SIZE 0x3ff80000 * * * ***************************************************************************************/ /* * Endpoint 0 */ #define Endp_NE0 (USB_Base + 0x504)#define Endp_NE0_Msk 0xffffffff #define Endp_NE0_Rst 0x00000000 /* Values ....*/ #define Endp_NE0_EPNUM 0x00000000#define Endp_NE0_EPDIR_OUT 0x00000000 #define Endp_NE0_EPDIR_IN 0x00000010 #define Endp_NE0_EPTYPE_CNTR 0x00000000 /* bidirectional control endpoint */ #define Endp_NE0_CFG_NUM 0x00000780 #define Endp_NE0_INTF_NUM 0x00007800 #define Endp_NE0_ALT_SETT 0x00078000 #define Endp_NE0_MAX_PKT_SIZE 0x02000000 /* 64 byte */ /* * Endpoint 1 */#define Endp_NE1 (USB_Base + 0x508)#define Endp_NE1_Msk 0xffffffff #define Endp_NE1_Rst 0x00000000 /* Values ....*/ #define Endp_NE1_EPNUM 0x00000001#define Endp_NE1_EPDIR_OUT 0x00000000 /* Bulk Out endpoint */ #define Endp_NE1_EPTYPE_BULK 0x00000040 #define Endp_NE1_CFG_NUM 0x00000780 #define Endp_NE1_INTF_NUM 0x00007800 #define Endp_NE1_ALT_SETT 0x00078000 #define Endp_NE1_MAX_PKT_SIZE 0x08000000 /* 512 byte *//* * Endpoint 2 */ #define Endp_NE2 (USB_Base + 0x50C)#define Endp_NE2_Msk 0xffffffff #define Endp_NE2_Rst 0x00000000 /* Values ....*/ #define Endp_NE2_EPNUM 0x00000002#define Endp_NE2_EPDIR_IN 0x00000010 /* Bulk In endpoint */ #define Endp_NE2_EPTYPE_BULK 0x00000040 #define Endp_NE2_CFG_NUM 0x00000780 #define Endp_NE2_INTF_NUM 0x00007800 #define Endp_NE2_ALT_SETT 0x00078000 #define Endp_NE2_MAX_PKT_SIZE 0x08000000 /* 512 byte */ /* Endpoint 3 */#define Endp_NE3 (USB_Base + 0x510)#define Endp_NE3_Msk 0xffffffff #define Endp_NE3_Rst 0x00000000 /* Values ....*/ #define Endp_NE3_EPNUM 0x00000003#define Endp_NE3_EPDIR_OUT 0x00000000 /* Bulk Out endpoint */ #define Endp_NE3_EPTYPE_BULK 0x00000040 #define Endp_NE3_CFG_NUM 0x00000780 #define Endp_NE3_INTF_NUM 0x00007800 #define Endp_NE3_ALT_SETT 0x00078000 #define Endp_NE3_MAX_PKT_SIZE 0x08000000 /* 512 byte */ /* Endpoint 4 */#define Endp_NE4 (USB_Base + 0x514)#define Endp_NE4_Msk 0xffffffff #define Endp_NE4_Rst 0x00000000 /* Values ....*/ #define Endp_NE4_EPNUM 0x00000004 #define Endp_NE4_EPDIR_IN 0x00000010 /* Bulk In endpoint */ #define Endp_NE4_EPTYPE_BULK 0x00000040 #define Endp_NE4_CFG_NUM 0x00000780 #define Endp_NE4_INTF_NUM 0x00007800 #define Endp_NE4_ALT_SETT 0x00078000 #define Endp_NE4_MAX_PKT_SIZE 0x08000000 /* 512 byte */ /* Endpoint 5 */#define Endp_NE5 (USB_Base + 0x518)#define Endp_NE5_Msk 0xffffffff #define Endp_NE5_Rst 0x00000000 /* Values ....*/ #define Endp_NE5_EPNUM 0x00000004 #define Endp_NE5_EPDIR_IN 0x00000010 /* Bulk In endpoint */ #define Endp_NE5_EPTYPE_BULK 0x00000040 #define Endp_NE5_CFG_NUM 0x00000780 #define Endp_NE5_INTF_NUM 0x00007800 #define Endp_NE5_ALT_SETT 0x00078000 #define Endp_NE5_MAX_PKT_SIZE 0x08000000 /* 512 byte */ /* * Configuration NC register: RO * A register is implemented for each supported configuration */ #define Conf_NC (USB_Base + 0x518)#define Conf_NC_Msk 0x00000000#define Conf_NC_Rst 0x00000000 /* Values ....*/ #define Conf_NC_CFG_DESC_ADDR_POINT 0x0000ffff#define Conf_NC_CFG_DESC_SIZE 0xffff0000 /* * String NS register: RO * A register is implemented for each supported string */ #define String_NS (USB_Base + 0x51C)#define String_NS_Msk 0x00000000#define String_NS_Rst 0x00000000 /* Values ....*/ #define String_NS_STR_DES_ADDR_POINT 0x0000ffff#define String_NS_STR_DES_SIZE 0x00ff0000 /* * Defines for Plug Detect */#define Plug_base (USB_Base + 0x00008000)#define Plug_state (Plug_base+0x0)#define Plug_Status_en (unsigned int)0x1#define Plug_Status_attached (unsigned int)0x2#define Plug_Status_phy_reset (unsigned int)0x4#define Plug_Status_phy_mode (unsigned int)0x8#define Plug_pending (Plug_base+0x4)#define Plug_intpend (unsigned int)0x1/* * FIFOs */#define USB_EP0_IN_BUSIZE 64 // IN#define USB_EP1_IN_BUSIZE 512#define USB_EP2_IN_BUSIZE 1024#define USB_EP0_OUT_BUSIZE 64 // OUT is 384 words (1536 bytes)#define USB_EP1_OUT_BUSIZE 960#define USB_EP2_OUT_BUSIZE 512 #define USB_RX_FIFO_Ep0 (USB_Base + 0x800)#define USB_RX_FIFO_Ep1 (USB_RX_FIFO_Ep0 + USB_EP0_OUT_BUSIZE) #define USB_RX_FIFO_Ep2 (USB_RX_FIFO_Ep1 + USB_EP1_OUT_BUSIZE ) #define USB_TX_FIFO (USB_Base + 0xE00)/* Before was:#define USB_TX_FIFO_DONE (USB_Base + 0x41c)*/#define USB_TX_FIFO_0_DONE (USB_Base + 0x01c)#define USB_TX_FIFO_1_DONE (USB_Base + 0x03c)#define USB_TX_FIFO_2_DONE (USB_Base + 0x05c)#define USB_RX_FIFO_0_DONE (USB_Base + 0x21c)#define USB_RX_FIFO_1_DONE (USB_Base + 0x23c)#define USB_RX_FIFO_2_DONE (USB_Base + 0x25c)#ifdef __cplusplus} /* C declarations in C++ */#endifvoid init_usb();void * memcpy(void * dest,const void *src,size_t count);#endif // __SPEAr_USB_H⌨️ 快捷键说明
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