mpmc_pl175_sdr.s.svn-base

Spearhead2000 的 USB驱动程序

    ;	 apBIT_BUILD( PL175_DYNAMIC_CONTROL_DE,   apPL175_DLL_HANDSHAKING_DISABLED )  |
    ;	 apBIT_BUILD( PL175_DYNAMIC_CONTROL_DP,   apPL175_NORMAL_OPERATION )  |
    ;	 apBIT_BUILD( PL175_DYNAMIC_CONTROL_NRP,  apPL175_RP_HIGH )	      |
    ;	 apBIT_BUILD( PL175_DYNAMIC_CONTROL_RPV,  apPL175_RPVHH_NORMAL );

    LDR     a2, =0x408b
    LDR     a1, =MPMCDynamicControl
    STR     a2, [a1, #0]

    ;;;;;;;;;;;;;;;;;;;;;;;;;;;;
    ; Reset Mode config for dynamic #0
    ;;;;;;;;;;;;;;;;;;;;;;;;;;;;
    
    ; /* Perform read to each device.						        
    ;  * required for DDR memories to remove reset DLL bit 			        
    ;  * The address of the read is used to configure the SDRAM memories mode register 
    ;  */									        
    ; if( pInitial->uDDRResetModeConfig[ 0 ] != 0 )				        
    ; {										        
    ; 	 (void) *((volatile UWORD32 *) pInitial->uDDRResetModeConfig[ I ]);	        
    ; }										        
    ;     

    ;LDR     a1, =uDDRResetModeConfig
    ;CMP     a1, #0x0
    ;LDRNE   a2, [a1, #0]
    
    ;/* Select Normal mode, clear Dynamic memory clock enable */
    ;((PL175_sRegisters *) eBase)->DynamicControl =
    ;	 apBIT_BUILD( PL175_DYNAMIC_CONTROL_CE,   apPL175_CLK_DRIVEN_HIGH )   |
    ;	 apBIT_BUILD( PL175_DYNAMIC_CONTROL_CS,   apPL175_CLKOUT_RUNS ) |
    ;	 apBIT_BUILD( PL175_DYNAMIC_CONTROL_SR,   apPL175_NORMAL_MODE )       |
    ;	 apBIT_BUILD( PL175_DYNAMIC_CONTROL_SRMCC,  apPL175_CLKOUT_SREF_RUN )	|
    ;	 apBIT_BUILD( PL175_DYNAMIC_CONTROL_IMCC, apPL175_NCLKOUT_ENABLED )   |
    ;	 apBIT_BUILD( PL175_DYNAMIC_CONTROL_MCC,  apPL175_CLKOUT_ENABLED )    |
    ;	 apBIT_BUILD( PL175_DYNAMIC_CONTROL_I,    apPL175_INIT_NORMAL )       |
    ;	 apBIT_BUILD( PL175_DYNAMIC_CONTROL_DC,   apPL175_DLL_HANDSHAKING_DISABLED )  |
    ;	 apBIT_BUILD( PL175_DYNAMIC_CONTROL_DE,   apPL175_DLL_HANDSHAKING_DISABLED )  |
    ;	 apBIT_BUILD( PL175_DYNAMIC_CONTROL_DP,   apPL175_NORMAL_OPERATION )  |
    ;	 apBIT_BUILD( PL175_DYNAMIC_CONTROL_NRP,  apPL175_RP_HIGH )	      |
    ;	 apBIT_BUILD( PL175_DYNAMIC_CONTROL_RPV,  apPL175_RPVHH_NORMAL );

    LDR     a2, =0x400b
    LDR     a1, =MPMCDynamicControl
    STR     a2, [a1, #0]

    ;/* Initialise Static Memory registers for all banks */
    ;for( I = 0; I < 4; I++)      
    ;{
    ;    if(pInitial->StaticConfigEnable[ I ] == TRUE)
    ;    { 
    ;       apPL175_StaticMemoryConfigSet( oId, I, &pInitial->sConfig.sStaticConfig[ I ] );
    ;    }
    ;}

    ;/* Program MPMCStaticExtendedWait register*/
    ;((PL175_sRegisters *) eBase)->StaticExtendedWait = pInitial->sConfig.StaticExtendedWait;

;Programming Dyn 1 GIO
    LDR     a2, =PL175_RAS_CAS_LATENCY
    LDR     a1, =MPMCDynamicRasCas1
    STR     a2, [a1, #0]

	 LDR     a2, =PL175_CONFIG1
    LDR     a1, =MPMCDynamicConfig1
    STR     a2, [a1, #0]
 
    LDR     a2, =0x408b
    LDR     a1, =MPMCDynamicControl
    STR     a2, [a1, #0]

    LDR     a1, =uSDRAMExtModeConfig1
    CMP     a1, #0x0
    LDRNE   a2, [a1, #0]

    LDR     a1, =uSDRAMModeConfig1
    CMP     a1, #0x0
    LDRNE   a2, [a1, #0]
            
    LDR     a1, =PAUSE_MEM_INIT
	 ;BL      TimerWait
	 
    LDR     a2, =0x410b
    LDR     a1, =MPMCDynamicControl
    STR     a2, [a1, #0]

    LDR     a1, =PAUSE_REFRESH_INIT
    ;BL      TimerWait

    LDR     a2, =0x408b
    LDR     a1, =MPMCDynamicControl
    STR     a2, [a1, #0]
	 
    LDR     a2, =0x400b
    LDR     a1, =MPMCDynamicControl
    STR     a2, [a1, #0]

;Programming Dyn 2 GIO
    LDR     a2, =PL175_RAS_CAS_LATENCY
    LDR     a1, =MPMCDynamicRasCas2
    STR     a2, [a1, #0]
    
    LDR     a2, =PL175_CONFIG2
    LDR     a1, =MPMCDynamicConfig2
    STR     a2, [a1, #0]
 
    LDR     a2, =0x408b
    LDR     a1, =MPMCDynamicControl
    STR     a2, [a1, #0]

    LDR     a1, =uSDRAMExtModeConfig2
    CMP     a1, #0x0
    LDRNE   a2, [a1, #0]

    LDR     a1, =uSDRAMModeConfig2
    CMP     a1, #0x0
    LDRNE   a2, [a1, #0]
            
    LDR     a1, =PAUSE_MEM_INIT
	 ;BL      TimerWait
	 
    LDR     a2, =0x410b
    LDR     a1, =MPMCDynamicControl
    STR     a2, [a1, #0]

    LDR     a1, =PAUSE_REFRESH_INIT
    ;BL      TimerWait

    LDR     a2, =0x408b
    LDR     a1, =MPMCDynamicControl
    STR     a2, [a1, #0]
	 
    LDR     a2, =0x400b
    LDR     a1, =MPMCDynamicControl
    STR     a2, [a1, #0]

;Programming Dyn 3 GIO
	 LDR     a2, =PL175_RAS_CAS_LATENCY
    LDR     a1, =MPMCDynamicRasCas3
    STR     a2, [a1, #0]

    LDR     a2, =PL175_CONFIG3
    LDR     a1, =MPMCDynamicConfig3
    STR     a2, [a1, #0]
 
    LDR     a2, =0x408b
    LDR     a1, =MPMCDynamicControl
    STR     a2, [a1, #0]

    LDR     a1, =uSDRAMExtModeConfig3
    CMP     a1, #0x0
    LDRNE   a2, [a1, #0]

    LDR     a1, =uSDRAMModeConfig3
    CMP     a1, #0x0
    LDRNE   a2, [a1, #0]
            
    LDR     a1, =PAUSE_MEM_INIT
	 ;BL      TimerWait
	 
    LDR     a2, =0x410b
    LDR     a1, =MPMCDynamicControl
    STR     a2, [a1, #0]

    LDR     a1, =PAUSE_REFRESH_INIT
    ;BL      TimerWait

    LDR     a2, =0x408b
    LDR     a1, =MPMCDynamicControl
    STR     a2, [a1, #0]
	 
    LDR     a2, =0x400b
    LDR     a1, =MPMCDynamicControl
    STR     a2, [a1, #0]




    ;  return();
    ;
    MOV		pc, v1      ; Restore lr
      
;}

;-------------------------------------------------------------------------------
; USE TIMER2 for MPMC PL175 programming
;-------------------------------------------------------------------------------

TIMER       EQU	0x12000000


; timer2 registers
TIMER_CONTROL2    EQU	TIMER + 0x100
TIMER_STATUS2     EQU	TIMER + 0x104
TIMER_INT_ACK2    EQU	TIMER + 0x104
TIMER_COMPARE2    EQU	TIMER + 0x108
TIMER_COUNT2      EQU	TIMER + 0x10C
TIMER_REDG_CAPT2  EQU	TIMER + 0x110       ;not used
TIMER_FEDG_CAPT2  EQU	TIMER + 0x114

;	Detailed Registers Naming
TIMER_PRESCAL     EQU	0x00F	
TIMER_MODE        EQU	0x010	
TIMER_ENAB        EQU	0x020	
TIMER_NO_CAPT     EQU	0x000
TIMER_RE_CAPT     EQU	0x040
TIMER_FE_CAPT     EQU	0x080
TIMER_RF_CAPT     EQU	0x0C0
TIMER_MATCH_INT   EQU	0x100	
TIMER_FEDG_INT    EQU	0x200	
TIMER_REDG_INT    EQU	0x400	
TIMER_MATCH       EQU	0x001   
TIMER_FEDG        EQU	0x002   
TIMER_REDG        EQU	0x004   

;
; This routine uses the TIMER2 to wait for 'val' microseconds.
; Please note that at this stage the timer is clocked with 10MHz clock 
; (cycle time is 100 nsec).
;
;VOID  TimerWait(UINT32 val)
;{

TimerWait

    ; a1 keeps the 'val' parameter
    LDR     a2, =TIMER_CONTROL2  ; keep the timer_control2 register address in a2

    ; turn the timer off (just in case ...)
    ; GPTCntl->TIMER_2_CONTROL_REG &= ~GPT_ENAB; 
    MOV     a4, #0x0
    STR     a4, [a2, #0]
    
    ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
    ; Enable timer2, but do not use the prescaler (unit is 100 ns)
    ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
    ; GPTCntl->TIMER_2_CONTROL_REG  |=  GPT_ENAB | GPT_AUTO_RELOAD; 
    MOV     a4, #0x20
    STR     a4, [a2, #0]

    ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
    ; Wait until timer2 reaches 'val'
    ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

    MOV     a3, #10
    MUL     a4, a1, a3   ; Since 'val' isn usec unit but timer2 unit is in 100 nsec, we
                     ; need to multiply it by ten.

    MOV     a1, a4

    LDR     a3, =TIMER_COUNT2    ; keep the timer_count2 register address in a3
loop
    LDR     a4, [a3, #0]
    CMP     a4, a1
    BLT     loop
    
    ; turn the timer off
    ; GPTCntl->TIMER_2_CONTROL_REG &= ~GPT_ENAB; 
    MOV     a4, #0x0
    STR     a4, [a2, #0]

    ;  return();
    ;
    MOV		pc, lr      ; Restore lr
      
;}

	END